1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AM6: SoC specific initialization
4 *
5 * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
7 */
8
9 #include <fdt_support.h>
10 #include <init.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <spl.h>
14 #include <asm/arch/hardware.h>
15 #include <dm.h>
16 #include <dm/uclass-internal.h>
17 #include <dm/pinctrl.h>
18 #include <linux/soc/ti/ti_sci_protocol.h>
19 #include <log.h>
20 #include <mmc.h>
21 #include <stdlib.h>
22
23 #include "../sysfw-loader.h"
24 #include "../common.h"
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 #ifdef CONFIG_K3_LOAD_SYSFW
29 struct fwl_data main_cbass_fwls[] = {
30 { "MMCSD1_CFG", 2057, 1 },
31 { "MMCSD0_CFG", 2058, 1 },
32 { "USB3SS0_SLV0", 2176, 2 },
33 { "PCIE0_SLV", 2336, 8 },
34 { "PCIE1_SLV", 2337, 8 },
35 { "PCIE0_CFG", 2688, 1 },
36 { "PCIE1_CFG", 2689, 1 },
37 }, mcu_cbass_fwls[] = {
38 { "MCU_ARMSS0_CORE0_SLV", 1024, 1 },
39 { "MCU_ARMSS0_CORE1_SLV", 1028, 1 },
40 { "MCU_FSS0_S1", 1033, 8 },
41 { "MCU_FSS0_S0", 1036, 8 },
42 { "MCU_CPSW0", 1220, 1 },
43 };
44 #endif
45
ctrl_mmr_unlock(void)46 static void ctrl_mmr_unlock(void)
47 {
48 /* Unlock all WKUP_CTRL_MMR0 module registers */
49 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
50 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
51 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
52 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
53 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
54 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
55
56 /* Unlock all MCU_CTRL_MMR0 module registers */
57 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
58 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
59 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
60 mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
61
62 /* Unlock all CTRL_MMR0 module registers */
63 mmr_unlock(CTRL_MMR0_BASE, 0);
64 mmr_unlock(CTRL_MMR0_BASE, 1);
65 mmr_unlock(CTRL_MMR0_BASE, 2);
66 mmr_unlock(CTRL_MMR0_BASE, 3);
67 mmr_unlock(CTRL_MMR0_BASE, 6);
68 mmr_unlock(CTRL_MMR0_BASE, 7);
69 }
70
71 /*
72 * This uninitialized global variable would normal end up in the .bss section,
73 * but the .bss is cleared between writing and reading this variable, so move
74 * it to the .data section.
75 */
76 u32 bootindex __section(".data");
77
store_boot_index_from_rom(void)78 static void store_boot_index_from_rom(void)
79 {
80 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
81 }
82
83 #if defined(CONFIG_K3_LOAD_SYSFW) && CONFIG_IS_ENABLED(DM_MMC)
k3_mmc_stop_clock(void)84 void k3_mmc_stop_clock(void)
85 {
86 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
87 struct mmc *mmc = find_mmc_device(0);
88
89 if (!mmc)
90 return;
91
92 mmc->saved_clock = mmc->clock;
93 mmc_set_clock(mmc, 0, true);
94 }
95 }
96
k3_mmc_restart_clock(void)97 void k3_mmc_restart_clock(void)
98 {
99 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
100 struct mmc *mmc = find_mmc_device(0);
101
102 if (!mmc)
103 return;
104
105 mmc_set_clock(mmc, mmc->saved_clock, false);
106 }
107 }
108 #else
k3_mmc_stop_clock(void)109 void k3_mmc_stop_clock(void) {}
k3_mmc_restart_clock(void)110 void k3_mmc_restart_clock(void) {}
111 #endif
112 #if CONFIG_IS_ENABLED(DFU) || CONFIG_IS_ENABLED(USB_STORAGE)
113 #define CTRLMMR_SERDES0_CTRL 0x00104080
114 #define PCIE_LANE0 0x1
fixup_usb_boot(void)115 static int fixup_usb_boot(void)
116 {
117 int ret;
118
119 switch (spl_boot_device()) {
120 case BOOT_DEVICE_USB:
121 /*
122 * If bootmode is Host bootmode, fixup the dr_mode to host
123 * before the dwc3 bind takes place
124 */
125 ret = fdt_find_and_setprop((void *)gd->fdt_blob,
126 "/bus@100000/dwc3@4000000/usb@10000",
127 "dr_mode", "host", 5, 0);
128 if (ret)
129 printf("%s: fdt_find_and_setprop() failed:%d\n", __func__,
130 ret);
131 fallthrough;
132 case BOOT_DEVICE_DFU:
133 /*
134 * The serdes mux between PCIe and USB3 needs to be set to PCIe for
135 * accessing the interface at USB 2.0
136 */
137 writel(PCIE_LANE0, CTRLMMR_SERDES0_CTRL);
138 default:
139 break;
140 }
141
142 return 0;
143 }
144
fdtdec_board_setup(const void * fdt_blob)145 int fdtdec_board_setup(const void *fdt_blob)
146 {
147 return fixup_usb_boot();
148 }
149 #endif
150
setup_am654_navss_northbridge(void)151 static void setup_am654_navss_northbridge(void)
152 {
153 /*
154 * NB0 is bridge to SRAM and NB1 is bridge to DDR.
155 * To ensure that SRAM transfers are not stalled due to
156 * delays during DDR refreshes, SRAM traffic should be higher
157 * priority (threadmap=2) than DDR traffic (threadmap=0).
158 */
159 writel(0x2, NAVSS0_NBSS_NB0_CFG_BASE + NAVSS_NBSS_THREADMAP);
160 writel(0x0, NAVSS0_NBSS_NB1_CFG_BASE + NAVSS_NBSS_THREADMAP);
161 }
162
board_init_f(ulong dummy)163 void board_init_f(ulong dummy)
164 {
165 #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
166 struct udevice *dev;
167 size_t pool_size;
168 void *pool_addr;
169 int ret;
170 #endif
171 /*
172 * Cannot delay this further as there is a chance that
173 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
174 */
175 store_boot_index_from_rom();
176
177 /* Make all control module registers accessible */
178 ctrl_mmr_unlock();
179
180 setup_am654_navss_northbridge();
181
182 #ifdef CONFIG_CPU_V7R
183 disable_linefill_optimization();
184 setup_k3_mpu_regions();
185 #endif
186
187 /* Init DM early in-order to invoke system controller */
188 spl_early_init();
189
190 #ifdef CONFIG_K3_EARLY_CONS
191 /*
192 * Allow establishing an early console as required for example when
193 * doing a UART-based boot. Note that this console may not "survive"
194 * through a SYSFW PM-init step and will need a re-init in some way
195 * due to changing module clock frequencies.
196 */
197 early_console_init();
198 #endif
199
200 #ifdef CONFIG_K3_LOAD_SYSFW
201 /*
202 * Initialize an early full malloc environment. Do so by allocating a
203 * new malloc area inside the currently active pre-relocation "first"
204 * malloc pool of which we use all that's left.
205 */
206 pool_size = CONFIG_VAL(SYS_MALLOC_F_LEN) - gd->malloc_ptr;
207 pool_addr = malloc(pool_size);
208 if (!pool_addr)
209 panic("ERROR: Can't allocate full malloc pool!\n");
210
211 mem_malloc_init((ulong)pool_addr, (ulong)pool_size);
212 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
213 debug("%s: initialized an early full malloc pool at 0x%08lx of 0x%lx bytes\n",
214 __func__, (unsigned long)pool_addr, (unsigned long)pool_size);
215 /*
216 * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
217 * regardless of the result of pinctrl. Do this without probing the
218 * device, but instead by searching the device that would request the
219 * given sequence number if probed. The UART will be used by the system
220 * firmware (SYSFW) image for various purposes and SYSFW depends on us
221 * to initialize its pin settings.
222 */
223 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
224 if (!ret)
225 pinctrl_select_state(dev, "default");
226
227 /*
228 * Load, start up, and configure system controller firmware while
229 * also populating the SYSFW post-PM configuration callback hook.
230 */
231 k3_sysfw_loader(false, k3_mmc_stop_clock, k3_mmc_restart_clock);
232
233 /* Prepare console output */
234 preloader_console_init();
235
236 /* Disable ROM configured firewalls right after loading sysfw */
237 remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls));
238 remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls));
239 #else
240 /* Prepare console output */
241 preloader_console_init();
242 #endif
243
244 /* Output System Firmware version info */
245 k3_sysfw_print_ver();
246
247 /* Perform board detection */
248 do_board_detect();
249
250 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
251 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
252 &dev);
253 if (ret)
254 printf("AVS init failed: %d\n", ret);
255 #endif
256
257 #ifdef CONFIG_K3_AM654_DDRSS
258 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
259 if (ret)
260 panic("DRAM init failed: %d\n", ret);
261 #endif
262 spl_enable_cache();
263 }
264
spl_mmc_boot_mode(struct mmc * mmc,const u32 boot_device)265 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
266 {
267 #if defined(CONFIG_SUPPORT_EMMC_BOOT)
268 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
269
270 u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
271 CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
272
273 /* eMMC boot0 mode is only supported for primary boot */
274 if (bootindex == K3_PRIMARY_BOOTMODE &&
275 bootmode == BOOT_DEVICE_MMC1)
276 return MMCSD_MODE_EMMCBOOT;
277 #endif
278
279 /* Everything else use filesystem if available */
280 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
281 return MMCSD_MODE_FS;
282 #else
283 return MMCSD_MODE_RAW;
284 #endif
285 }
286
__get_backup_bootmedia(u32 devstat)287 static u32 __get_backup_bootmedia(u32 devstat)
288 {
289 u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
290 CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
291
292 switch (bkup_boot) {
293 case BACKUP_BOOT_DEVICE_USB:
294 return BOOT_DEVICE_USB;
295 case BACKUP_BOOT_DEVICE_UART:
296 return BOOT_DEVICE_UART;
297 case BACKUP_BOOT_DEVICE_ETHERNET:
298 return BOOT_DEVICE_ETHERNET;
299 case BACKUP_BOOT_DEVICE_MMC2:
300 {
301 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
302 CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
303 if (port == 0x0)
304 return BOOT_DEVICE_MMC1;
305 return BOOT_DEVICE_MMC2;
306 }
307 case BACKUP_BOOT_DEVICE_SPI:
308 return BOOT_DEVICE_SPI;
309 case BACKUP_BOOT_DEVICE_HYPERFLASH:
310 return BOOT_DEVICE_HYPERFLASH;
311 case BACKUP_BOOT_DEVICE_I2C:
312 return BOOT_DEVICE_I2C;
313 };
314
315 return BOOT_DEVICE_RAM;
316 }
317
__get_primary_bootmedia(u32 devstat)318 static u32 __get_primary_bootmedia(u32 devstat)
319 {
320 u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
321 CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
322
323 if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
324 bootmode = BOOT_DEVICE_SPI;
325
326 if (bootmode == BOOT_DEVICE_MMC2) {
327 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
328 CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
329 if (port == 0x0)
330 bootmode = BOOT_DEVICE_MMC1;
331 } else if (bootmode == BOOT_DEVICE_MMC1) {
332 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
333 CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
334 if (port == 0x1)
335 bootmode = BOOT_DEVICE_MMC2;
336 } else if (bootmode == BOOT_DEVICE_DFU) {
337 u32 mode = (devstat & CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK) >>
338 CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT;
339 if (mode == 0x2)
340 bootmode = BOOT_DEVICE_USB;
341 }
342
343 return bootmode;
344 }
345
spl_boot_device(void)346 u32 spl_boot_device(void)
347 {
348 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
349
350 if (bootindex == K3_PRIMARY_BOOTMODE)
351 return __get_primary_bootmedia(devstat);
352 else
353 return __get_backup_bootmedia(devstat);
354 }
355