1 // SPDX-License-Identifier:     GPL-2.0+
2 /*
3  * K3: ARM64 MMU setup
4  *
5  * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
6  *	Lokesh Vutla <lokeshvutla@ti.com>
7  *	Suman Anna <s-anna@ti.com>
8  * (This file is derived from arch/arm/mach-zynqmp/cpu.c)
9  *
10  */
11 
12 #include <asm/system.h>
13 #include <asm/armv8/mmu.h>
14 
15 struct mm_region k3_mem_map[] = {
16 	{
17 		.virt = 0x0UL,
18 		.phys = 0x0UL,
19 		.size = 0x80000000UL,
20 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
21 			 PTE_BLOCK_NON_SHARE |
22 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
23 	}, {
24 		.virt = 0x80000000UL,
25 		.phys = 0x80000000UL,
26 		.size = 0x1e780000UL,
27 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
28 			 PTE_BLOCK_INNER_SHARE
29 	}, {
30 		.virt = 0xa0000000UL,
31 		.phys = 0xa0000000UL,
32 		.size = 0x60000000UL,
33 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
34 			 PTE_BLOCK_INNER_SHARE
35 	}, {
36 		.virt = 0x880000000UL,
37 		.phys = 0x880000000UL,
38 		.size = 0x80000000UL,
39 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
40 			 PTE_BLOCK_INNER_SHARE
41 	}, {
42 		.virt = 0x500000000UL,
43 		.phys = 0x500000000UL,
44 		.size = 0x380000000UL,
45 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
46 			 PTE_BLOCK_NON_SHARE |
47 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
48 	}, {
49 		/* List terminator */
50 		0,
51 	}
52 };
53 
54 struct mm_region *mem_map = k3_mem_map;
55