1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ 4 * Lokesh Vutla <lokeshvutla@ti.com> 5 */ 6 #ifndef _ASM_ARCH_HARDWARE_H_ 7 #define _ASM_ARCH_HARDWARE_H_ 8 9 #include <asm/io.h> 10 11 #ifdef CONFIG_SOC_K3_AM625 12 #include "am62_hardware.h" 13 #endif 14 15 #ifdef CONFIG_SOC_K3_AM62A7 16 #include "am62a_hardware.h" 17 #endif 18 19 #ifdef CONFIG_SOC_K3_AM62P5 20 #include "am62p_hardware.h" 21 #endif 22 23 #ifdef CONFIG_SOC_K3_AM642 24 #include "am64_hardware.h" 25 #endif 26 27 #ifdef CONFIG_SOC_K3_AM654 28 #include "am6_hardware.h" 29 #endif 30 31 #ifdef CONFIG_SOC_K3_J721E 32 #include "j721e_hardware.h" 33 #endif 34 35 #ifdef CONFIG_SOC_K3_J7200 36 #include "j721e_hardware.h" 37 #endif 38 39 #ifdef CONFIG_SOC_K3_J721S2 40 #include "j721s2_hardware.h" 41 #endif 42 43 #ifdef CONFIG_SOC_K3_J722S 44 #include "j722s_hardware.h" 45 #endif 46 47 #ifdef CONFIG_SOC_K3_J784S4 48 #include "j784s4_hardware.h" 49 #endif 50 51 52 /* Assuming these addresses and definitions stay common across K3 devices */ 53 #define CTRLMMR_WKUP_JTAG_ID (WKUP_CTRL_MMR0_BASE + 0x14) 54 #define JTAG_ID_VARIANT_SHIFT 28 55 #define JTAG_ID_VARIANT_MASK (0xf << 28) 56 #define JTAG_ID_PARTNO_SHIFT 12 57 #define JTAG_ID_PARTNO_MASK (0xffff << 12) 58 #define JTAG_ID_PARTNO_AM62AX 0xbb8d 59 #define JTAG_ID_PARTNO_AM62PX 0xbb9d 60 #define JTAG_ID_PARTNO_AM62X 0xbb7e 61 #define JTAG_ID_PARTNO_AM64X 0xbb38 62 #define JTAG_ID_PARTNO_AM65X 0xbb5a 63 #define JTAG_ID_PARTNO_J7200 0xbb6d 64 #define JTAG_ID_PARTNO_J721E 0xbb64 65 #define JTAG_ID_PARTNO_J721S2 0xbb75 66 #define JTAG_ID_PARTNO_J722S 0xbba0 67 #define JTAG_ID_PARTNO_J784S4 0xbb80 68 69 #define CTRLMMR_WKUP_JTAG_DEVICE_ID (WKUP_CTRL_MMR0_BASE + 0x18) 70 #define JTAG_DEV_J742S2_PKG_MASK GENMASK(2, 0) 71 #define JTAG_DEV_J742S2_PKG_SHIFT 0 72 73 #define JTAG_ID_PKG_J742S2 0x7 74 75 #define K3_SOC_ID(id, ID) \ 76 static inline bool soc_is_##id(void) \ 77 { \ 78 u32 soc = (readl(CTRLMMR_WKUP_JTAG_ID) & \ 79 JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT; \ 80 return soc == JTAG_ID_PARTNO_##ID; \ 81 } 82 K3_SOC_ID(am62x, AM62X) 83 K3_SOC_ID(am62ax, AM62AX) 84 K3_SOC_ID(am62px, AM62PX) 85 K3_SOC_ID(am64x, AM64X) 86 K3_SOC_ID(am65x, AM65X) 87 K3_SOC_ID(j7200, J7200) 88 K3_SOC_ID(j721e, J721E) 89 K3_SOC_ID(j721s2, J721S2) 90 K3_SOC_ID(j722s, J722S) 91 92 #define K3_SEC_MGR_SYS_STATUS 0x44234100 93 #define SYS_STATUS_DEV_TYPE_SHIFT 0 94 #define SYS_STATUS_DEV_TYPE_MASK (0xf) 95 #define SYS_STATUS_DEV_TYPE_GP 0x3 96 #define SYS_STATUS_DEV_TYPE_TEST 0x5 97 #define SYS_STATUS_DEV_TYPE_EMU 0x9 98 #define SYS_STATUS_DEV_TYPE_HS 0xa 99 #define SYS_STATUS_SUB_TYPE_SHIFT 8 100 #define SYS_STATUS_SUB_TYPE_MASK (0xf << 8) 101 #define SYS_STATUS_SUB_TYPE_VAL_FS 0xa 102 103 /* 104 * The CTRL_MMR0 memory space is divided into several equally-spaced 105 * partitions, so defining the partition size allows us to determine 106 * register addresses common to those partitions. 107 */ 108 #define CTRL_MMR0_PARTITION_SIZE 0x4000 109 110 /* 111 * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism 112 * shared register definitions. The same registers are also used for 113 * PADCFG_MMR lock/kick-mechanism. 114 */ 115 #define CTRLMMR_LOCK_KICK0 0x1008 116 #define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 117 #define CTRLMMR_LOCK_KICK1 0x100c 118 #define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a 119 120 #define K3_ROM_BOOT_HEADER_MAGIC "EXTBOOT" 121 122 struct rom_extended_boot_data { 123 char header[8]; 124 u32 num_components; 125 }; 126 127 u32 get_boot_device(void); 128 const char *get_reset_reason(void); 129 #endif /* _ASM_ARCH_HARDWARE_H_ */ 130