1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2021 Pali Rohár <pali@kernel.org>
4 * Copyright (C) 2024 Marek Behún <kabel@kernel.org>
5 */
6
7 #include <dm.h>
8 #include <dm/lists.h>
9 #include <regmap.h>
10 #include <reset-uclass.h>
11 #include <syscon.h>
12 #include <sysreset.h>
13 #include <asm/io.h>
14
15 #define MVEBU_SOC_CONTROL_1_REG 0x4
16
17 #if defined(CONFIG_ARMADA_375)
18 # define MVEBU_RSTOUTN_MASK_REG 0x54
19 # define MVEBU_SYS_SOFT_RST_REG 0x58
20 #else
21 # define MVEBU_RSTOUTN_MASK_REG 0x60
22 # define MVEBU_SYS_SOFT_RST_REG 0x64
23 #endif
24
25 #define MVEBU_GLOBAL_SOFT_RST_BIT BIT(0)
26
27 #define MVEBU_PCIE_ID 0
28
29 #if IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET)
30
mvebu_reset_of_xlate(struct reset_ctl * rst,struct ofnode_phandle_args * args)31 static int mvebu_reset_of_xlate(struct reset_ctl *rst,
32 struct ofnode_phandle_args *args)
33 {
34 if (args->args_count < 2)
35 return -EINVAL;
36
37 rst->id = args->args[0];
38 rst->data = args->args[1];
39
40 /* Currently only PCIe is implemented */
41 if (rst->id != MVEBU_PCIE_ID)
42 return -EINVAL;
43
44 /* Four PCIe enable bits are shared across more PCIe links */
45 if (!(rst->data >= 0 && rst->data <= 3))
46 return -EINVAL;
47
48 return 0;
49 }
50
mvebu_reset_request(struct reset_ctl * rst)51 static int mvebu_reset_request(struct reset_ctl *rst)
52 {
53 return 0;
54 }
55
mvebu_reset_free(struct reset_ctl * rst)56 static int mvebu_reset_free(struct reset_ctl *rst)
57 {
58 return 0;
59 }
60
mvebu_reset_assert(struct reset_ctl * rst)61 static int mvebu_reset_assert(struct reset_ctl *rst)
62 {
63 struct regmap *regmap = syscon_get_regmap(rst->dev->parent);
64
65 return regmap_update_bits(regmap, MVEBU_SOC_CONTROL_1_REG,
66 BIT(rst->data), 0);
67 }
68
mvebu_reset_deassert(struct reset_ctl * rst)69 static int mvebu_reset_deassert(struct reset_ctl *rst)
70 {
71 struct regmap *regmap = syscon_get_regmap(rst->dev->parent);
72
73 return regmap_update_bits(regmap, MVEBU_SOC_CONTROL_1_REG,
74 BIT(rst->data), BIT(rst->data));
75 }
76
mvebu_reset_status(struct reset_ctl * rst)77 static int mvebu_reset_status(struct reset_ctl *rst)
78 {
79 struct regmap *regmap = syscon_get_regmap(rst->dev->parent);
80 uint val;
81 int ret;
82
83 ret = regmap_read(regmap, MVEBU_SOC_CONTROL_1_REG, &val);
84 if (ret < 0)
85 return ret;
86
87 return !(val & BIT(rst->data));
88 }
89
90 static const struct reset_ops mvebu_reset_ops = {
91 .of_xlate = mvebu_reset_of_xlate,
92 .request = mvebu_reset_request,
93 .rfree = mvebu_reset_free,
94 .rst_assert = mvebu_reset_assert,
95 .rst_deassert = mvebu_reset_deassert,
96 .rst_status = mvebu_reset_status,
97 };
98
99 U_BOOT_DRIVER(mvebu_reset) = {
100 .name = "mvebu-reset",
101 .id = UCLASS_RESET,
102 .ops = &mvebu_reset_ops,
103 };
104
105 #endif /* IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET) */
106
107 #if IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET)
108
mvebu_sysreset_request(struct udevice * dev,enum sysreset_t type)109 static int mvebu_sysreset_request(struct udevice *dev, enum sysreset_t type)
110 {
111 struct regmap *regmap = syscon_get_regmap(dev->parent);
112 uint bit;
113
114 if (type != SYSRESET_COLD)
115 return -EPROTONOSUPPORT;
116
117 bit = MVEBU_GLOBAL_SOFT_RST_BIT;
118
119 regmap_update_bits(regmap, MVEBU_RSTOUTN_MASK_REG, bit, bit);
120 regmap_update_bits(regmap, MVEBU_SYS_SOFT_RST_REG, bit, bit);
121
122 /* Loop while waiting for the reset */
123 while (1)
124 ;
125
126 return 0;
127 }
128
129 static struct sysreset_ops mvebu_sysreset_ops = {
130 .request = mvebu_sysreset_request,
131 };
132
133 U_BOOT_DRIVER(mvebu_sysreset) = {
134 .name = "mvebu-sysreset",
135 .id = UCLASS_SYSRESET,
136 .ops = &mvebu_sysreset_ops,
137 };
138
139 #endif /* IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET) */
140
mvebu_syscon_bind(struct udevice * dev)141 static int mvebu_syscon_bind(struct udevice *dev)
142 {
143 int ret = 0;
144
145 /* bind also mvebu-reset, with the same ofnode */
146 if (IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET)) {
147 ret = device_bind_driver_to_node(dev, "mvebu-reset",
148 "mvebu-reset", dev_ofnode(dev),
149 NULL);
150 if (ret < 0)
151 return ret;
152 }
153
154 /* bind also mvebu-sysreset, with the same ofnode */
155 if (IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET)) {
156 ret = device_bind_driver_to_node(dev, "mvebu-sysreset",
157 "mvebu-sysreset",
158 dev_ofnode(dev), NULL);
159 if (ret < 0)
160 return ret;
161 }
162
163 return ret;
164 }
165
166 static const struct udevice_id mvebu_syscon_of_match[] = {
167 { .compatible = "marvell,armada-370-xp-system-controller" },
168 { .compatible = "marvell,armada-375-system-controller" },
169 { .compatible = "marvell,armada-380-system-controller" },
170 { .compatible = "marvell,armada-390-system-controller" },
171 { },
172 };
173
174 U_BOOT_DRIVER(mvebu_syscon) = {
175 .name = "mvebu-system-controller",
176 .id = UCLASS_SYSCON,
177 .of_match = mvebu_syscon_of_match,
178 .bind = mvebu_syscon_bind,
179 };
180