1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
4 */
5
6 #include <asm/arch/clock_manager.h>
7 #include <asm/arch/system_manager.h>
8 #include <asm/global_data.h>
9 #include <asm/io.h>
10 #include <command.h>
11 #include <init.h>
12 #include <wait_bit.h>
13
14 DECLARE_GLOBAL_DATA_PTR;
15
cm_wait_for_lock(u32 mask)16 void cm_wait_for_lock(u32 mask)
17 {
18 u32 inter_val;
19 u32 retry = 0;
20 do {
21 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
22 inter_val = readl(socfpga_get_clkmgr_addr() +
23 CLKMGR_INTER) & mask;
24 #else
25 inter_val = readl(socfpga_get_clkmgr_addr() +
26 CLKMGR_STAT) & mask;
27 #endif
28 /* Wait for stable lock */
29 if (inter_val == mask)
30 retry++;
31 else
32 retry = 0;
33 if (retry >= 10)
34 break;
35 } while (1);
36 }
37
38 /* function to poll in the fsm busy bit */
cm_wait_for_fsm(void)39 int cm_wait_for_fsm(void)
40 {
41 return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() +
42 CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 20000,
43 false);
44 }
45
set_cpu_clk_info(void)46 int set_cpu_clk_info(void)
47 {
48 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
49 /* Calculate the clock frequencies required for drivers */
50 cm_get_l4_sp_clk_hz();
51 cm_get_mmc_controller_clk_hz();
52 #endif
53
54 gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
55 gd->bd->bi_dsp_freq = 0;
56
57 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
58 gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
59 #else
60 gd->bd->bi_ddr_freq = 0;
61 #endif
62
63 return 0;
64 }
65
66 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
cm_set_qspi_controller_clk_hz(u32 clk_hz)67 int cm_set_qspi_controller_clk_hz(u32 clk_hz)
68 {
69 u32 reg;
70 u32 clk_khz;
71
72 /*
73 * Store QSPI ref clock and set into sysmgr boot register.
74 * Only clock freq in kHz degree is accepted due to limited bits[27:0]
75 * is reserved for storing the QSPI clock freq into boot scratch cold0
76 * register.
77 */
78 if (clk_hz < 1000)
79 return -EINVAL;
80
81 clk_khz = clk_hz / 1000;
82 printf("QSPI: Reference clock at %d kHz\n", clk_khz);
83
84 reg = (readl(socfpga_get_sysmgr_addr() +
85 SYSMGR_SOC64_BOOT_SCRATCH_COLD0)) &
86 ~(SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK);
87
88 writel((clk_khz & SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) | reg,
89 socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
90
91 return 0;
92 }
93
cm_get_qspi_controller_clk_hz(void)94 unsigned int cm_get_qspi_controller_clk_hz(void)
95 {
96 return (readl(socfpga_get_sysmgr_addr() +
97 SYSMGR_SOC64_BOOT_SCRATCH_COLD0) &
98 SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) * 1000;
99 }
100 #endif
101
102 #ifndef CONFIG_XPL_BUILD
do_showclocks(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])103 static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
104 char *const argv[])
105 {
106 cm_print_clock_quick_summary();
107 return 0;
108 }
109
110 U_BOOT_CMD(
111 clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,
112 "display clocks",
113 ""
114 );
115 #endif
116