1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2013-2025 Altera Corporation <www.altera.com> 4 */ 5 6 #ifndef _CLOCK_MANAGER_H_ 7 #define _CLOCK_MANAGER_H_ 8 9 #include <linux/types.h> 10 11 phys_addr_t socfpga_get_clkmgr_addr(void); 12 13 #ifndef __ASSEMBLY__ 14 void cm_wait_for_lock(u32 mask); 15 int cm_wait_for_fsm(void); 16 void cm_print_clock_quick_summary(void); 17 unsigned long cm_get_mpu_clk_hz(void); 18 unsigned int cm_get_qspi_controller_clk_hz(void); 19 20 #if defined(CONFIG_TARGET_SOCFPGA_SOC64) 21 int cm_set_qspi_controller_clk_hz(u32 clk_hz); 22 #endif 23 #endif 24 25 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 26 #include <asm/arch/clock_manager_gen5.h> 27 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 28 #include <asm/arch/clock_manager_arria10.h> 29 #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) 30 #include <asm/arch/clock_manager_s10.h> 31 #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) 32 #include <asm/arch/clock_manager_agilex.h> 33 #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) 34 #include <asm/arch/clock_manager_agilex5.h> 35 #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) 36 #include <asm/arch/clock_manager_n5x.h> 37 #endif 38 39 #endif /* _CLOCK_MANAGER_H_ */ 40