1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #include <log.h>
7 #include <asm/io.h>
8 #include <asm/arch/clock.h>
9 #include <asm/arch/flow.h>
10 #include <asm/arch/tegra.h>
11 #include <asm/arch-tegra/clk_rst.h>
12 #include <asm/arch-tegra/pmc.h>
13 #include <asm/arch-tegra/tegra_i2c.h>
14 #include <linux/delay.h>
15 #include "../cpu.h"
16
17 /* In case this function is not defined */
pmic_enable_cpu_vdd(void)18 __weak void pmic_enable_cpu_vdd(void) {}
19
enable_cpu_power_rail(void)20 static void enable_cpu_power_rail(void)
21 {
22 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
23 u32 reg;
24
25 debug("enable_cpu_power_rail entry\n");
26 reg = readl(&pmc->pmc_cntrl);
27 reg |= CPUPWRREQ_OE;
28 writel(reg, &pmc->pmc_cntrl);
29 }
30
31 /**
32 * The T30 requires some special clock initialization, including setting up
33 * the dvc i2c, turning on mselect and selecting the G CPU cluster
34 */
t30_init_clocks(void)35 void t30_init_clocks(void)
36 {
37 struct clk_rst_ctlr *clkrst =
38 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
39 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
40 u32 val;
41
42 debug("t30_init_clocks entry\n");
43 /* Set active CPU cluster to G */
44 clrbits_le32(flow->cluster_control, 1 << 0);
45
46 writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
47
48 val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
49 (1 << CLK_SYS_RATE_AHB_RATE_SHIFT) |
50 (0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) |
51 (0 << CLK_SYS_RATE_APB_RATE_SHIFT);
52 writel(val, &clkrst->crc_clk_sys_rate);
53
54 /* Put i2c, mselect in reset and enable clocks */
55 reset_set_enable(PERIPH_ID_DVC_I2C, 1);
56 clock_set_enable(PERIPH_ID_DVC_I2C, 1);
57 reset_set_enable(PERIPH_ID_MSELECT, 1);
58 clock_set_enable(PERIPH_ID_MSELECT, 1);
59
60 /* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */
61 clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2);
62
63 /*
64 * Our high-level clock routines are not available prior to
65 * relocation. We use the low-level functions which require a
66 * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17)
67 */
68 clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C, 3, 16);
69
70 /*
71 * Give clocks time to stabilize, then take i2c and mselect out of
72 * reset
73 */
74 udelay(1000);
75 reset_set_enable(PERIPH_ID_DVC_I2C, 0);
76 reset_set_enable(PERIPH_ID_MSELECT, 0);
77 }
78
set_cpu_running(int run)79 static void set_cpu_running(int run)
80 {
81 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
82
83 debug("set_cpu_running entry, run = %d\n", run);
84 writel(run ? FLOW_MODE_NONE : FLOW_MODE_STOP, &flow->halt_cpu_events);
85 }
86
start_cpu(u32 reset_vector)87 void start_cpu(u32 reset_vector)
88 {
89 debug("start_cpu entry, reset_vector = %x\n", reset_vector);
90 t30_init_clocks();
91
92 /* Enable VDD_CPU */
93 enable_cpu_power_rail();
94 pmic_enable_cpu_vdd();
95
96 set_cpu_running(0);
97
98 /* Hold the CPUs in reset */
99 reset_A9_cpu(1);
100
101 /* Disable the CPU clock */
102 enable_cpu_clock(0);
103
104 /* Enable CoreSight */
105 clock_enable_coresight(1);
106
107 /*
108 * Set the entry point for CPU execution from reset,
109 * if it's a non-zero value.
110 */
111 if (reset_vector)
112 writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
113
114 /* Enable the CPU clock */
115 enable_cpu_clock(1);
116
117 /* If the CPU doesn't already have power, power it up */
118 powerup_cpu();
119
120 /* Take the CPU out of reset */
121 reset_A9_cpu(0);
122
123 set_cpu_running(1);
124 }
125