1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Panasonic Corporation
4 * Copyright (C) 2015-2017 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 */
7
8 #include <command.h>
9 #include <stdio.h>
10 #include <linux/io.h>
11 #include <linux/printk.h>
12 #include <linux/sizes.h>
13 #include <linux/string.h>
14
15 #include "../soc-info.h"
16 #include "ddrphy-regs.h"
17
18 /* Select either decimal or hexadecimal */
19 #if 1
20 #define PRINTF_FORMAT "%2d"
21 #else
22 #define PRINTF_FORMAT "%02x"
23 #endif
24 /* field separator */
25 #define FS " "
26
27 #define ptr_to_uint(p) ((unsigned int)(unsigned long)(p))
28
29 #define UNIPHIER_MAX_NR_DDRPHY 4
30
31 struct uniphier_ddrphy_param {
32 unsigned int soc_id;
33 unsigned int nr_phy;
34 struct {
35 resource_size_t base;
36 unsigned int nr_dx;
37 } phy[UNIPHIER_MAX_NR_DDRPHY];
38 };
39
40 static const struct uniphier_ddrphy_param uniphier_ddrphy_param[] = {
41 {
42 .soc_id = UNIPHIER_LD4_ID,
43 .nr_phy = 2,
44 .phy = {
45 { .base = 0x5bc01000, .nr_dx = 2, },
46 { .base = 0x5be01000, .nr_dx = 2, },
47 },
48 },
49 {
50 .soc_id = UNIPHIER_PRO4_ID,
51 .nr_phy = 4,
52 .phy = {
53 { .base = 0x5bc01000, .nr_dx = 2, },
54 { .base = 0x5bc02000, .nr_dx = 2, },
55 { .base = 0x5be01000, .nr_dx = 2, },
56 { .base = 0x5be02000, .nr_dx = 2, },
57 },
58 },
59 {
60 .soc_id = UNIPHIER_SLD8_ID,
61 .nr_phy = 2,
62 .phy = {
63 { .base = 0x5bc01000, .nr_dx = 2, },
64 { .base = 0x5be01000, .nr_dx = 2, },
65 },
66 },
67 {
68 .soc_id = UNIPHIER_LD11_ID,
69 .nr_phy = 1,
70 .phy = {
71 { .base = 0x5bc01000, .nr_dx = 4, },
72 },
73 },
74 };
UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_ddrphy_param,uniphier_ddrphy_param)75 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_ddrphy_param, uniphier_ddrphy_param)
76
77 static void print_bdl(void __iomem *reg, int n)
78 {
79 u32 val = readl(reg);
80 int i;
81
82 for (i = 0; i < n; i++)
83 printf(FS PRINTF_FORMAT, (val >> i * 6) & 0x3f);
84 }
85
dump_loop(const struct uniphier_ddrphy_param * param,void (* callback)(void __iomem *))86 static void dump_loop(const struct uniphier_ddrphy_param *param,
87 void (*callback)(void __iomem *))
88 {
89 void __iomem *phy_base, *dx_base;
90 int phy, dx;
91
92 for (phy = 0; phy < param->nr_phy; phy++) {
93 phy_base = ioremap(param->phy[phy].base, SZ_4K);
94 dx_base = phy_base + PHY_DX_BASE;
95
96 for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
97 printf("PHY%dDX%d:", phy, dx);
98 (*callback)(dx_base);
99 dx_base += PHY_DX_STRIDE;
100 printf("\n");
101 }
102
103 iounmap(phy_base);
104 }
105 }
106
__wbdl_dump(void __iomem * dx_base)107 static void __wbdl_dump(void __iomem *dx_base)
108 {
109 print_bdl(dx_base + PHY_DX_BDLR0, 5);
110 print_bdl(dx_base + PHY_DX_BDLR1, 5);
111
112 printf(FS "(+" PRINTF_FORMAT ")",
113 readl(dx_base + PHY_DX_LCDLR1) & 0xff);
114 }
115
wbdl_dump(const struct uniphier_ddrphy_param * param)116 static void wbdl_dump(const struct uniphier_ddrphy_param *param)
117 {
118 printf("\n--- Write Bit Delay Line ---\n");
119 printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
120
121 dump_loop(param, &__wbdl_dump);
122 }
123
__rbdl_dump(void __iomem * dx_base)124 static void __rbdl_dump(void __iomem *dx_base)
125 {
126 print_bdl(dx_base + PHY_DX_BDLR3, 5);
127 print_bdl(dx_base + PHY_DX_BDLR4, 4);
128
129 printf(FS "(+" PRINTF_FORMAT ")",
130 (readl(dx_base + PHY_DX_LCDLR1) >> 8) & 0xff);
131 }
132
rbdl_dump(const struct uniphier_ddrphy_param * param)133 static void rbdl_dump(const struct uniphier_ddrphy_param *param)
134 {
135 printf("\n--- Read Bit Delay Line ---\n");
136 printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
137
138 dump_loop(param, &__rbdl_dump);
139 }
140
__wld_dump(void __iomem * dx_base)141 static void __wld_dump(void __iomem *dx_base)
142 {
143 int rank;
144 u32 lcdlr0 = readl(dx_base + PHY_DX_LCDLR0);
145 u32 gtr = readl(dx_base + PHY_DX_GTR);
146
147 for (rank = 0; rank < 4; rank++) {
148 u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
149 u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
150
151 printf(FS PRINTF_FORMAT "%sT", wld,
152 wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
153 }
154 }
155
wld_dump(const struct uniphier_ddrphy_param * param)156 static void wld_dump(const struct uniphier_ddrphy_param *param)
157 {
158 printf("\n--- Write Leveling Delay ---\n");
159 printf(" Rank0 Rank1 Rank2 Rank3\n");
160
161 dump_loop(param, &__wld_dump);
162 }
163
__dqsgd_dump(void __iomem * dx_base)164 static void __dqsgd_dump(void __iomem *dx_base)
165 {
166 int rank;
167 u32 lcdlr2 = readl(dx_base + PHY_DX_LCDLR2);
168 u32 gtr = readl(dx_base + PHY_DX_GTR);
169
170 for (rank = 0; rank < 4; rank++) {
171 u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
172 u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
173
174 printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
175 }
176 }
177
dqsgd_dump(const struct uniphier_ddrphy_param * param)178 static void dqsgd_dump(const struct uniphier_ddrphy_param *param)
179 {
180 printf("\n--- DQS Gating Delay ---\n");
181 printf(" Rank0 Rank1 Rank2 Rank3\n");
182
183 dump_loop(param, &__dqsgd_dump);
184 }
185
__mdl_dump(void __iomem * dx_base)186 static void __mdl_dump(void __iomem *dx_base)
187 {
188 int i;
189 u32 mdl = readl(dx_base + PHY_DX_MDLR);
190
191 for (i = 0; i < 3; i++)
192 printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
193 }
194
mdl_dump(const struct uniphier_ddrphy_param * param)195 static void mdl_dump(const struct uniphier_ddrphy_param *param)
196 {
197 printf("\n--- Master Delay Line ---\n");
198 printf(" IPRD TPRD MDLD\n");
199
200 dump_loop(param, &__mdl_dump);
201 }
202
203 #define REG_DUMP(x) \
204 { int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst; \
205 printf("%3d: %-10s: %08x : %08x\n", \
206 ofst >> PHY_REG_SHIFT, #x, \
207 ptr_to_uint(reg), readl(reg)); }
208
209 #define DX_REG_DUMP(dx, x) \
210 { int ofst = PHY_DX_BASE + PHY_DX_STRIDE * (dx) + \
211 PHY_DX_## x; \
212 void __iomem *reg = phy_base + ofst; \
213 printf("%3d: DX%d%-7s: %08x : %08x\n", \
214 ofst >> PHY_REG_SHIFT, (dx), #x, \
215 ptr_to_uint(reg), readl(reg)); }
216
reg_dump(const struct uniphier_ddrphy_param * param)217 static void reg_dump(const struct uniphier_ddrphy_param *param)
218 {
219 void __iomem *phy_base;
220 int phy, dx;
221
222 printf("\n--- DDR PHY registers ---\n");
223
224 for (phy = 0; phy < param->nr_phy; phy++) {
225 phy_base = ioremap(param->phy[phy].base, SZ_4K);
226
227 printf("== PHY%d (base: %08x) ==\n",
228 phy, ptr_to_uint(phy_base));
229 printf(" No: Name : Address : Data\n");
230
231 REG_DUMP(RIDR);
232 REG_DUMP(PIR);
233 REG_DUMP(PGCR0);
234 REG_DUMP(PGCR1);
235 REG_DUMP(PGSR0);
236 REG_DUMP(PGSR1);
237 REG_DUMP(PLLCR);
238 REG_DUMP(PTR0);
239 REG_DUMP(PTR1);
240 REG_DUMP(PTR2);
241 REG_DUMP(PTR3);
242 REG_DUMP(PTR4);
243 REG_DUMP(ACMDLR);
244 REG_DUMP(ACBDLR);
245 REG_DUMP(DXCCR);
246 REG_DUMP(DSGCR);
247 REG_DUMP(DCR);
248 REG_DUMP(DTPR0);
249 REG_DUMP(DTPR1);
250 REG_DUMP(DTPR2);
251 REG_DUMP(MR0);
252 REG_DUMP(MR1);
253 REG_DUMP(MR2);
254 REG_DUMP(MR3);
255
256 for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
257 DX_REG_DUMP(dx, GCR);
258 DX_REG_DUMP(dx, GTR);
259 }
260
261 iounmap(phy_base);
262 }
263 }
264
do_ddr(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])265 static int do_ddr(struct cmd_tbl *cmdtp, int flag, int argc,
266 char *const argv[])
267 {
268 const struct uniphier_ddrphy_param *param;
269 char *cmd;
270
271 param = uniphier_get_ddrphy_param();
272 if (!param) {
273 pr_err("unsupported SoC\n");
274 return CMD_RET_FAILURE;
275 }
276
277 if (argc == 1)
278 cmd = "all";
279 else
280 cmd = argv[1];
281
282 if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
283 wbdl_dump(param);
284
285 if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
286 rbdl_dump(param);
287
288 if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
289 wld_dump(param);
290
291 if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
292 dqsgd_dump(param);
293
294 if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
295 mdl_dump(param);
296
297 if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
298 reg_dump(param);
299
300 return CMD_RET_SUCCESS;
301 }
302
303 U_BOOT_CMD(
304 ddr, 2, 1, do_ddr,
305 "UniPhier DDR PHY parameters dumper",
306 "- dump all of the following\n"
307 "ddr wbdl - dump Write Bit Delay\n"
308 "ddr rbdl - dump Read Bit Delay\n"
309 "ddr wld - dump Write Leveling\n"
310 "ddr dqsgd - dump DQS Gating Delay\n"
311 "ddr mdl - dump Master Delay Line\n"
312 "ddr reg - dump registers\n"
313 );
314