1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 *
4 * (C) Copyright 2000-2003
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
8 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 */
10
11 #include <cpu_func.h>
12 #include <init.h>
13 #include <watchdog.h>
14 #include <asm/immap.h>
15 #include <asm/processor.h>
16 #include <asm/rtc.h>
17 #include <asm/io.h>
18 #include <linux/compiler.h>
19
20 #if defined(CONFIG_CMD_NET)
21 #include <config.h>
22 #include <net.h>
23 #include <asm/fec.h>
24 #endif
25
init_fbcs(void)26 void init_fbcs(void)
27 {
28 fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
29
30 #if !defined(CONFIG_SERIAL_BOOT)
31 #if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL))
32 out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
33 out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
34 out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
35 #endif
36 #endif
37
38 #if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL))
39 /* Latch chipselect */
40 out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
41 out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
42 out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
43 #endif
44
45 #if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL))
46 out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
47 out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
48 out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
49 #endif
50
51 #if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL))
52 out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
53 out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
54 out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
55 #endif
56
57 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
58 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
59 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
60 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
61 #endif
62
63 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
64 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
65 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
66 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
67 #endif
68 }
69
70 #ifdef CONFIG_CF_DSPI
cfspi_port_conf(void)71 void cfspi_port_conf(void)
72 {
73 gpio_t *gpio = (gpio_t *)MMAP_GPIO;
74
75 #ifdef CONFIG_MCF5441x
76 pm_t *pm = (pm_t *)MMAP_PM;
77
78 out_8(&gpio->par_dspi0,
79 GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
80 GPIO_PAR_DSPI0_SCK_DSPI0SCK);
81 out_8(&gpio->srcr_dspiow, 3);
82
83 /* DSPI0 */
84 out_8(&pm->pmcr0, 23);
85 #endif
86 }
87 #endif
88
89 /*
90 * Breath some life into the CPU...
91 *
92 * Set up the memory map,
93 * initialize a bunch of registers,
94 * initialize the UPM's
95 */
cpu_init_f(void)96 void cpu_init_f(void)
97 {
98 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
99
100 #ifdef CONFIG_MCF5441x
101 scm_t *scm = (scm_t *) MMAP_SCM;
102 pm_t *pm = (pm_t *) MMAP_PM;
103
104 /* Disable Switch */
105 *(unsigned long *)(MMAP_L2_SW0 + 0x00000024) = 0;
106
107 /* Disable core watchdog */
108 out_be16(&scm->cwcr, 0);
109 out_8(&gpio->par_fbctl,
110 GPIO_PAR_FBCTL_ALE_FB_ALE | GPIO_PAR_FBCTL_OE_FB_OE |
111 GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW |
112 GPIO_PAR_FBCTL_TA_TA);
113 out_8(&gpio->par_be,
114 GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
115 GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
116
117 /* eDMA */
118 out_8(&pm->pmcr0, 17);
119
120 /* INTR0 - INTR2 */
121 out_8(&pm->pmcr0, 18);
122 out_8(&pm->pmcr0, 19);
123 out_8(&pm->pmcr0, 20);
124
125 /* I2C */
126 out_8(&pm->pmcr0, 22);
127 out_8(&pm->pmcr1, 4);
128 out_8(&pm->pmcr1, 7);
129
130 /* DTMR0 - DTMR3*/
131 out_8(&pm->pmcr0, 28);
132 out_8(&pm->pmcr0, 29);
133 out_8(&pm->pmcr0, 30);
134 out_8(&pm->pmcr0, 31);
135
136 /* PIT0 - PIT3 */
137 out_8(&pm->pmcr0, 32);
138 out_8(&pm->pmcr0, 33);
139 out_8(&pm->pmcr0, 34);
140 out_8(&pm->pmcr0, 35);
141
142 /* Edge Port */
143 out_8(&pm->pmcr0, 36);
144 out_8(&pm->pmcr0, 37);
145
146 /* USB OTG */
147 out_8(&pm->pmcr0, 44);
148 /* USB Host */
149 out_8(&pm->pmcr0, 45);
150
151 /* ESDHC */
152 out_8(&pm->pmcr0, 51);
153
154 /* ENET0 - ENET1 */
155 out_8(&pm->pmcr0, 53);
156 out_8(&pm->pmcr0, 54);
157
158 /* NAND */
159 out_8(&pm->pmcr0, 63);
160
161 #ifdef CFG_SYS_I2C_0
162 out_8(&gpio->par_cani2c, 0xF0);
163 /* I2C0 pull up */
164 out_be16(&gpio->pcr_b, 0x003C);
165 /* I2C0 max speed */
166 out_8(&gpio->srcr_cani2c, 0x03);
167 #endif
168 #ifdef CFG_SYS_I2C_2
169 /* I2C2 */
170 out_8(&gpio->par_ssi0h, 0xA0);
171 /* I2C2, UART7 */
172 out_8(&gpio->par_ssi0h, 0xA8);
173 /* UART7 */
174 out_8(&gpio->par_ssi0l, 0x2);
175 /* UART8, UART9 */
176 out_8(&gpio->par_cani2c, 0xAA);
177 /* UART4, UART0 */
178 out_8(&gpio->par_uart0, 0xAF);
179 /* UART5, UART1 */
180 out_8(&gpio->par_uart1, 0xAF);
181 /* UART6, UART2 */
182 out_8(&gpio->par_uart2, 0xAF);
183 /* I2C2 pull up */
184 out_be16(&gpio->pcr_h, 0xF000);
185 #endif
186 #ifdef CFG_SYS_I2C_5
187 /* I2C5 */
188 out_8(&gpio->par_uart1, 0x0A);
189 /* I2C5 pull up */
190 out_be16(&gpio->pcr_e, 0x0003);
191 out_be16(&gpio->pcr_f, 0xC000);
192 #endif
193
194 /* Lowest slew rate for UART0,1,2 */
195 out_8(&gpio->srcr_uart, 0x00);
196
197 #ifdef CONFIG_FSL_ESDHC_IMX
198 /* eSDHC pin as faster speed */
199 out_8(&gpio->srcr_sdhc, 0x03);
200
201 /* All esdhc pins as SD */
202 out_8(&gpio->par_sdhch, 0xff);
203 out_8(&gpio->par_sdhcl, 0xff);
204 #endif
205 #endif /* CONFIG_MCF5441x */
206
207 /* FlexBus Chipselect */
208 init_fbcs();
209
210 #ifdef CFG_SYS_CS0_BASE
211 /*
212 * now the flash base address is no longer at 0 (Newer ColdFire family
213 * boot at address 0 instead of 0xFFnn_nnnn). The vector table must
214 * also move to the new location.
215 */
216 if (CFG_SYS_CS0_BASE != 0)
217 setvbr(CFG_SYS_CS0_BASE);
218 #endif
219
220 icache_enable();
221 }
222
223 /*
224 * initialize higher level parts of CPU like timers
225 */
cpu_init_r(void)226 int cpu_init_r(void)
227 {
228 #ifdef CONFIG_MCFRTC
229 rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
230 rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
231
232 out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
233 out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
234 #endif
235
236 return (0);
237 }
238
uart_port_conf(int port)239 void uart_port_conf(int port)
240 {
241 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
242 #ifdef CONFIG_MCF5441x
243 pm_t *pm = (pm_t *) MMAP_PM;
244 #endif
245
246 /* Setup Ports: */
247 switch (port) {
248 #ifdef CONFIG_MCF5441x
249 case 0:
250 /* UART0 */
251 out_8(&pm->pmcr0, 24);
252 clrbits_8(&gpio->par_uart0,
253 ~(GPIO_PAR_UART0_U0RXD_MASK | GPIO_PAR_UART0_U0TXD_MASK));
254 setbits_8(&gpio->par_uart0,
255 GPIO_PAR_UART0_U0RXD_U0RXD | GPIO_PAR_UART0_U0TXD_U0TXD);
256 break;
257 case 1:
258 /* UART1 */
259 out_8(&pm->pmcr0, 25);
260 clrbits_8(&gpio->par_uart1,
261 ~(GPIO_PAR_UART1_U1RXD_MASK | GPIO_PAR_UART1_U1TXD_MASK));
262 setbits_8(&gpio->par_uart1,
263 GPIO_PAR_UART1_U1RXD_U1RXD | GPIO_PAR_UART1_U1TXD_U1TXD);
264 break;
265 case 2:
266 /* UART2 */
267 out_8(&pm->pmcr0, 26);
268 clrbits_8(&gpio->par_uart2,
269 ~(GPIO_PAR_UART2_U2RXD_MASK | GPIO_PAR_UART2_U2TXD_MASK));
270 setbits_8(&gpio->par_uart2,
271 GPIO_PAR_UART2_U2RXD_U2RXD | GPIO_PAR_UART2_U2TXD_U2TXD);
272 break;
273 case 3:
274 /* UART3 */
275 out_8(&pm->pmcr0, 27);
276 clrbits_8(&gpio->par_dspi0,
277 ~(GPIO_PAR_DSPI0_SIN_MASK | GPIO_PAR_DSPI0_SOUT_MASK));
278 setbits_8(&gpio->par_dspi0,
279 GPIO_PAR_DSPI0_SIN_U3RXD | GPIO_PAR_DSPI0_SOUT_U3TXD);
280 break;
281 case 4:
282 /* UART4 */
283 out_8(&pm->pmcr1, 24);
284 clrbits_8(&gpio->par_uart0,
285 ~(GPIO_PAR_UART0_U0CTS_MASK | GPIO_PAR_UART0_U0RTS_MASK));
286 setbits_8(&gpio->par_uart0,
287 GPIO_PAR_UART0_U0CTS_U4TXD | GPIO_PAR_UART0_U0RTS_U4RXD);
288 break;
289 case 5:
290 /* UART5 */
291 out_8(&pm->pmcr1, 25);
292 clrbits_8(&gpio->par_uart1,
293 ~(GPIO_PAR_UART1_U1CTS_MASK | GPIO_PAR_UART1_U1RTS_MASK));
294 setbits_8(&gpio->par_uart1,
295 GPIO_PAR_UART1_U1CTS_U5TXD | GPIO_PAR_UART1_U1RTS_U5RXD);
296 break;
297 case 6:
298 /* UART6 */
299 out_8(&pm->pmcr1, 26);
300 clrbits_8(&gpio->par_uart2,
301 ~(GPIO_PAR_UART2_U2CTS_MASK | GPIO_PAR_UART2_U2RTS_MASK));
302 setbits_8(&gpio->par_uart2,
303 GPIO_PAR_UART2_U2CTS_U6TXD | GPIO_PAR_UART2_U2RTS_U6RXD);
304 break;
305 case 7:
306 /* UART7 */
307 out_8(&pm->pmcr1, 27);
308 clrbits_8(&gpio->par_ssi0h, ~GPIO_PAR_SSI0H_RXD_MASK);
309 clrbits_8(&gpio->par_ssi0l, ~GPIO_PAR_SSI0L_BCLK_MASK);
310 setbits_8(&gpio->par_ssi0h, GPIO_PAR_SSI0H_FS_U7TXD);
311 setbits_8(&gpio->par_ssi0l, GPIO_PAR_SSI0L_BCLK_U7RXD);
312 break;
313 case 8:
314 /* UART8 */
315 out_8(&pm->pmcr0, 28);
316 clrbits_8(&gpio->par_cani2c,
317 ~(GPIO_PAR_CANI2C_I2C0SCL_MASK | GPIO_PAR_CANI2C_I2C0SDA_MASK));
318 setbits_8(&gpio->par_cani2c,
319 GPIO_PAR_CANI2C_I2C0SCL_U8TXD | GPIO_PAR_CANI2C_I2C0SDA_U8RXD);
320 break;
321 case 9:
322 /* UART9 */
323 out_8(&pm->pmcr1, 29);
324 clrbits_8(&gpio->par_cani2c,
325 ~(GPIO_PAR_CANI2C_CAN1TX_MASK | GPIO_PAR_CANI2C_CAN1RX_MASK));
326 setbits_8(&gpio->par_cani2c,
327 GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
328 break;
329 #endif
330 }
331 }
332
333 #if defined(CONFIG_CMD_NET)
fecpin_setclear(fec_info_t * info,int setclear)334 int fecpin_setclear(fec_info_t *info, int setclear)
335 {
336 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
337 u32 fec0_base;
338
339 if (fec_get_base_addr(0, &fec0_base))
340 return -1;
341
342 #ifdef CONFIG_MCF5441x
343 if (setclear) {
344 out_8(&gpio->par_fec, 0x03);
345 out_8(&gpio->srcr_fec, 0x0F);
346 clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK,
347 GPIO_PAR_SIMP0H_DAT_GPIO);
348 clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK,
349 GPIO_PDDR_G4_OUTPUT);
350 clrbits_8(&gpio->podr_g, ~GPIO_PODR_G4_MASK);
351
352 } else
353 clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC_MASK);
354 #endif
355 return 0;
356 }
357 #endif
358