1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (C) 1994 - 2002 by Ralf Baechle
4 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
5 * Copyright (C) 2002 Maciej W. Rozycki
6 */
7 #ifndef _ASM_PGTABLE_BITS_H
8 #define _ASM_PGTABLE_BITS_H
9
10 /*
11 * Note that we shift the lower 32bits of each EntryLo[01] entry
12 * 6 bits to the left. That way we can convert the PFN into the
13 * physical address by a single 'and' operation and gain 6 additional
14 * bits for storing information which isn't present in a normal
15 * MIPS page table.
16 *
17 * Similar to the Alpha port, we need to keep track of the ref
18 * and mod bits in software. We have a software "yeah you can read
19 * from this page" bit, and a hardware one which actually lets the
20 * process read from the page. On the same token we have a software
21 * writable bit and the real hardware one which actually lets the
22 * process write to the page, this keeps a mod bit via the hardware
23 * dirty bit.
24 *
25 * Certain revisions of the R4000 and R5000 have a bug where if a
26 * certain sequence occurs in the last 3 instructions of an executable
27 * page, and the following page is not mapped, the cpu can do
28 * unpredictable things. The code (when it is written) to deal with
29 * this problem will be in the update_mmu_cache() code for the r4k.
30 */
31 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
32
33 /*
34 * The following bits are implemented by the TLB hardware
35 */
36 #define _PAGE_NO_EXEC_SHIFT 0
37 #define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT)
38 #define _PAGE_NO_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
39 #define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT)
40 #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
41 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
42 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
43 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
44 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
45 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
46 #define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
47 #define _CACHE_MASK (7 << _CACHE_SHIFT)
48
49 /*
50 * The following bits are implemented in software
51 */
52 #define _PAGE_PRESENT_SHIFT (24)
53 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
54 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
55 #define _PAGE_READ (1 << _PAGE_READ_SHIFT)
56 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
57 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
58 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
59 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
60 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
61 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
62
63 #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
64
65 /*
66 * Bits for extended EntryLo0/EntryLo1 registers
67 */
68 #define _PFNX_MASK 0xffffff
69
70 #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
71
72 /*
73 * The following bits are implemented in software
74 */
75 #define _PAGE_PRESENT_SHIFT (0)
76 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
77 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
78 #define _PAGE_READ (1 << _PAGE_READ_SHIFT)
79 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
80 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
81 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
82 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
83 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
84 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
85
86 /*
87 * The following bits are implemented by the TLB hardware
88 */
89 #define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 4)
90 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
91 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
92 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
93 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
94 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
95 #define _CACHE_UNCACHED_SHIFT (_PAGE_DIRTY_SHIFT + 1)
96 #define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT)
97 #define _CACHE_MASK _CACHE_UNCACHED
98
99 #define _PFN_SHIFT PAGE_SHIFT
100
101 #else
102 /*
103 * Below are the "Normal" R4K cases
104 */
105
106 /*
107 * The following bits are implemented in software
108 */
109 #define _PAGE_PRESENT_SHIFT 0
110 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
111 /* R2 or later cores check for RI/XI support to determine _PAGE_READ */
112 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
113 #define _PAGE_WRITE_SHIFT (_PAGE_PRESENT_SHIFT + 1)
114 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
115 #else
116 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
117 #define _PAGE_READ (1 << _PAGE_READ_SHIFT)
118 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
119 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
120 #endif
121 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
122 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
123 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
124 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
125
126 #if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
127 /* Huge TLB page */
128 #define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
129 #define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
130 #define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1)
131 #define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT)
132 #endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */
133
134 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
135 /* XI - page cannot be executed */
136 #ifdef _PAGE_SPLITTING_SHIFT
137 #define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
138 #else
139 #define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
140 #endif
141 #define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
142
143 /* RI - page cannot be read */
144 #define _PAGE_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
145 #define _PAGE_READ (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT))
146 #define _PAGE_NO_READ_SHIFT _PAGE_READ_SHIFT
147 #define _PAGE_NO_READ (cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0)
148 #endif /* defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) */
149
150 #if defined(_PAGE_NO_READ_SHIFT)
151 #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
152 #elif defined(_PAGE_SPLITTING_SHIFT)
153 #define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
154 #else
155 #define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
156 #endif
157 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
158
159 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
160 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
161 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
162 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
163 #define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
164 #define _CACHE_MASK (7 << _CACHE_SHIFT)
165
166 #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
167
168 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
169
170 #ifndef _PAGE_NO_EXEC
171 #define _PAGE_NO_EXEC 0
172 #endif
173 #ifndef _PAGE_NO_READ
174 #define _PAGE_NO_READ 0
175 #endif
176
177 #define _PAGE_SILENT_READ _PAGE_VALID
178 #define _PAGE_SILENT_WRITE _PAGE_DIRTY
179
180 #define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
181
182 /*
183 * The final layouts of the PTE bits are:
184 *
185 * 64-bit, R1 or earlier: CCC D V G [S H] M A W R P
186 * 32-bit, R1 or earler: CCC D V G M A W R P
187 * 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P
188 * 32-bit, R2 or later: CCC D V G RI/R XI M A W P
189 */
190
191 #ifndef __ASSEMBLY__
192 /*
193 * pte_to_entrylo converts a page table entry (PTE) into a Mips
194 * entrylo0/1 value.
195 */
pte_to_entrylo(unsigned long pte_val)196 static inline uint64_t pte_to_entrylo(unsigned long pte_val)
197 {
198 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
199 if (cpu_has_rixi) {
200 int sa;
201 #ifdef CONFIG_32BIT
202 sa = 31 - _PAGE_NO_READ_SHIFT;
203 #else
204 sa = 63 - _PAGE_NO_READ_SHIFT;
205 #endif
206 /*
207 * C has no way to express that this is a DSRL
208 * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily
209 * in the fast path this is done in assembly
210 */
211 return (pte_val >> _PAGE_GLOBAL_SHIFT) |
212 ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
213 }
214 #endif
215
216 return pte_val >> _PAGE_GLOBAL_SHIFT;
217 }
218 #endif
219
220 /*
221 * Cache attributes
222 */
223 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
224
225 #define _CACHE_CACHABLE_NONCOHERENT 0
226 #define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
227
228 #elif defined(CONFIG_CPU_SB1)
229
230 /* No penalty for being coherent on the SB1, so just
231 use it for "noncoherent" spaces, too. Shouldn't hurt. */
232
233 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
234
235 #elif defined(CONFIG_CPU_LOONGSON3)
236
237 /* Using COHERENT flag for NONCOHERENT doesn't hurt. */
238
239 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
240 #define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
241
242 #elif defined(CONFIG_MACH_INGENIC)
243
244 /* Ingenic uses the WA bit to achieve write-combine memory writes */
245 #define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
246
247 #endif
248
249 #ifndef _CACHE_CACHABLE_NO_WA
250 #define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT)
251 #endif
252 #ifndef _CACHE_CACHABLE_WA
253 #define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT)
254 #endif
255 #ifndef _CACHE_UNCACHED
256 #define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
257 #endif
258 #ifndef _CACHE_CACHABLE_NONCOHERENT
259 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)
260 #endif
261 #ifndef _CACHE_CACHABLE_CE
262 #define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT)
263 #endif
264 #ifndef _CACHE_CACHABLE_COW
265 #define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
266 #endif
267 #ifndef _CACHE_CACHABLE_CUW
268 #define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT)
269 #endif
270 #ifndef _CACHE_UNCACHED_ACCELERATED
271 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
272 #endif
273
274 #define __READABLE (_PAGE_SILENT_READ | _PAGE_READ | _PAGE_ACCESSED)
275 #define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)
276
277 #define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \
278 _PFN_MASK | _CACHE_MASK)
279
280 #endif /* _ASM_PGTABLE_BITS_H */
281