1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 */
5
6 #include <command.h>
7 #include <init.h>
8 #include <linux/compiler.h>
9 #include <fsl_errata.h>
10 #include <asm/processor.h>
11 #include <fsl_usb.h>
12 #include "fsl_corenet_serdes.h"
13
14 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
15 /*
16 * This work-around is implemented in PBI, so just check to see if the
17 * work-around was actually applied. To do this, we check for specific data
18 * at specific addresses in DCSR.
19 *
20 * Array offsets[] contains a list of offsets within DCSR. According to the
21 * erratum document, the value at each offset should be 2.
22 */
check_erratum_a4849(uint32_t svr)23 static void check_erratum_a4849(uint32_t svr)
24 {
25 void __iomem *dcsr = (void *)CFG_SYS_DCSRBAR + 0xb0000;
26 unsigned int i;
27
28 #if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
29 static const uint8_t offsets[] = {
30 0x50, 0x54, 0x58, 0x90, 0x94, 0x98
31 };
32 #endif
33 #ifdef CONFIG_ARCH_P4080
34 static const uint8_t offsets[] = {
35 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac
36 };
37 #endif
38 uint32_t x108; /* The value that should be at offset 0x108 */
39
40 for (i = 0; i < ARRAY_SIZE(offsets); i++) {
41 if (in_be32(dcsr + offsets[i]) != 2) {
42 printf("Work-around for Erratum A004849 is not enabled\n");
43 return;
44 }
45 }
46
47 #if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
48 x108 = 0x12;
49 #endif
50
51 #ifdef CONFIG_ARCH_P4080
52 /*
53 * For P4080, the erratum document says that the value at offset 0x108
54 * should be 0x12 on rev2, or 0x1c on rev3.
55 */
56 if (SVR_MAJ(svr) == 2)
57 x108 = 0x12;
58 if (SVR_MAJ(svr) == 3)
59 x108 = 0x1c;
60 #endif
61
62 if (in_be32(dcsr + 0x108) != x108) {
63 printf("Work-around for Erratum A004849 is not enabled\n");
64 return;
65 }
66
67 /* Everything matches, so the erratum work-around was applied */
68
69 printf("Work-around for Erratum A004849 enabled\n");
70 }
71 #endif
72
73 #ifdef CONFIG_SYS_FSL_ERRATUM_A004580
74 /*
75 * This work-around is implemented in PBI, so just check to see if the
76 * work-around was actually applied. To do this, we check for specific data
77 * at specific addresses in the SerDes register block.
78 *
79 * The work-around says that for each SerDes lane, write BnTTLCRy0 =
80 * 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000.
81
82 */
check_erratum_a4580(uint32_t svr)83 static void check_erratum_a4580(uint32_t svr)
84 {
85 const serdes_corenet_t __iomem *srds_regs =
86 (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
87 unsigned int lane;
88
89 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
90 if (serdes_lane_enabled(lane)) {
91 const struct serdes_lane __iomem *srds_lane =
92 &srds_regs->lane[serdes_get_lane_idx(lane)];
93
94 /*
95 * Verify that the values we were supposed to write in
96 * the PBI are actually there. Also, the lower 15
97 * bits of res4[3] should be the same as the upper 15
98 * bits of res4[1].
99 */
100 if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) ||
101 (in_be32(&srds_lane->res4[1]) != 0x880000) ||
102 (in_be32(&srds_lane->res4[3]) != 0x40000044)) {
103 printf("Work-around for Erratum A004580 is "
104 "not enabled\n");
105 return;
106 }
107 }
108 }
109
110 /* Everything matches, so the erratum work-around was applied */
111
112 printf("Work-around for Erratum A004580 enabled\n");
113 }
114 #endif
115
116 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
117 /*
118 * This workaround can be implemented in PBI, or by u-boot.
119 */
check_erratum_a007212(void)120 static void check_erratum_a007212(void)
121 {
122 u32 __iomem *plldgdcr = (void *)(CFG_SYS_DCSRBAR + 0x21c20);
123
124 if (in_be32(plldgdcr) & 0x1fe) {
125 /* check if PLL ratio is set by workaround */
126 puts("Work-around for Erratum A007212 enabled\n");
127 }
128 }
129 #endif
130
do_errata(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])131 static int do_errata(struct cmd_tbl *cmdtp, int flag, int argc,
132 char *const argv[])
133 {
134 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
135 extern int enable_cpu_a011_workaround;
136 #endif
137 __maybe_unused u32 svr = get_svr();
138
139 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
140 if (IS_SVR_REV(svr, 1, 0)) {
141 switch (SVR_SOC_VER(svr)) {
142 case SVR_P1013:
143 case SVR_P1022:
144 puts("Work-around for Erratum SATA A001 enabled\n");
145 }
146 }
147 #endif
148
149 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
150 puts("Work-around for Erratum SERDES8 enabled\n");
151 #endif
152 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9)
153 puts("Work-around for Erratum SERDES9 enabled\n");
154 #endif
155 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005)
156 puts("Work-around for Erratum SERDES-A005 enabled\n");
157 #endif
158 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
159 if (SVR_MAJ(svr) < 3)
160 puts("Work-around for Erratum CPU22 enabled\n");
161 #endif
162 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
163 /*
164 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
165 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
166 * The SVR has been checked by cpu_init_r().
167 */
168 if (enable_cpu_a011_workaround)
169 puts("Work-around for Erratum CPU-A011 enabled\n");
170 #endif
171 #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
172 puts("Work-around for Erratum CPU-A003999 enabled\n");
173 #endif
174 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
175 puts("Work-around for Erratum DDR-A003474 enabled\n");
176 #endif
177 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
178 puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
179 #endif
180 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111)
181 puts("Work-around for Erratum ESDHC111 enabled\n");
182 #endif
183 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
184 puts("Work-around for Erratum A004468 enabled\n");
185 #endif
186 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
187 puts("Work-around for Erratum ESDHC135 enabled\n");
188 #endif
189 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13)
190 if (SVR_MAJ(svr) < 3)
191 puts("Work-around for Erratum ESDHC13 enabled\n");
192 #endif
193 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001)
194 puts("Work-around for Erratum ESDHC-A001 enabled\n");
195 #endif
196 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
197 puts("Work-around for Erratum CPC-A002 enabled\n");
198 #endif
199 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
200 puts("Work-around for Erratum CPC-A003 enabled\n");
201 #endif
202 #ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
203 puts("Work-around for Erratum ELBC-A001 enabled\n");
204 #endif
205 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
206 puts("Work-around for Erratum DDR-A003 enabled\n");
207 #endif
208 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
209 puts("Work-around for Erratum DDR115 enabled\n");
210 #endif
211 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
212 puts("Work-around for Erratum DDR111 enabled\n");
213 puts("Work-around for Erratum DDR134 enabled\n");
214 #endif
215 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
216 puts("Work-around for Erratum IFC-A002769 enabled\n");
217 #endif
218 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
219 puts("Work-around for Erratum P1010-A003549 enabled\n");
220 #endif
221 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
222 puts("Work-around for Erratum IFC A-003399 enabled\n");
223 #endif
224 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
225 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
226 puts("Work-around for Erratum NMG DDR120 enabled\n");
227 #endif
228 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
229 puts("Work-around for Erratum NMG_LBC103 enabled\n");
230 #endif
231 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
232 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
233 puts("Work-around for Erratum NMG ETSEC129 enabled\n");
234 #endif
235 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
236 puts("Work-around for Erratum A004508 enabled\n");
237 #endif
238 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
239 puts("Work-around for Erratum A004510 enabled\n");
240 #endif
241 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
242 puts("Work-around for Erratum SRIO-A004034 enabled\n");
243 #endif
244 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
245 puts("Work-around for Erratum A004934 enabled\n");
246 #endif
247 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
248 if (IS_SVR_REV(svr, 1, 0))
249 puts("Work-around for Erratum A005871 enabled\n");
250 #endif
251 #ifdef CONFIG_SYS_FSL_ERRATUM_A006475
252 if (SVR_MAJ(get_svr()) == 1)
253 puts("Work-around for Erratum A006475 enabled\n");
254 #endif
255 #ifdef CONFIG_SYS_FSL_ERRATUM_A006384
256 if (SVR_MAJ(get_svr()) == 1)
257 puts("Work-around for Erratum A006384 enabled\n");
258 #endif
259 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
260 /* This work-around is implemented in PBI, so just check for it */
261 check_erratum_a4849(svr);
262 #endif
263 #ifdef CONFIG_SYS_FSL_ERRATUM_A004580
264 /* This work-around is implemented in PBI, so just check for it */
265 check_erratum_a4580(svr);
266 #endif
267 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
268 puts("Work-around for Erratum PCIe-A003 enabled\n");
269 #endif
270 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
271 puts("Work-around for Erratum USB14 enabled\n");
272 #endif
273 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186
274 if (has_erratum_a007186())
275 puts("Work-around for Erratum A007186 enabled\n");
276 #endif
277 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
278 puts("Work-around for Erratum A006593 enabled\n");
279 #endif
280 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
281 if (has_erratum_a006379())
282 puts("Work-around for Erratum A006379 enabled\n");
283 #endif
284 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
285 if (IS_SVR_REV(svr, 1, 0))
286 puts("Work-around for Erratum A003571 enabled\n");
287 #endif
288 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
289 puts("Work-around for Erratum A-005812 enabled\n");
290 #endif
291 #ifdef CONFIG_SYS_FSL_ERRATUM_A005125
292 puts("Work-around for Erratum A005125 enabled\n");
293 #endif
294 #ifdef CONFIG_SYS_FSL_ERRATUM_A007075
295 if (has_erratum_a007075())
296 puts("Work-around for Erratum A007075 enabled\n");
297 #endif
298 #ifdef CONFIG_SYS_FSL_ERRATUM_A007798
299 if (has_erratum_a007798())
300 puts("Work-around for Erratum A007798 enabled\n");
301 #endif
302 #ifdef CONFIG_SYS_FSL_ERRATUM_A004477
303 if (has_erratum_a004477())
304 puts("Work-around for Erratum A004477 enabled\n");
305 #endif
306 #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
307 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
308 (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
309 puts("Work-around for Erratum I2C-A004447 enabled\n");
310 #endif
311 #ifdef CONFIG_SYS_FSL_ERRATUM_A005275
312 if (has_erratum_a005275())
313 puts("Work-around for Erratum A005275 enabled\n");
314 #endif
315 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
316 if (has_erratum_a006261())
317 puts("Work-around for Erratum A006261 enabled\n");
318 #endif
319 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
320 check_erratum_a007212();
321 #endif
322 #ifdef CONFIG_SYS_FSL_ERRATUM_A005434
323 puts("Work-around for Erratum A-005434 enabled\n");
324 #endif
325 #if defined(CONFIG_SYS_FSL_ERRATUM_A008044) && \
326 defined(CONFIG_A008044_WORKAROUND)
327 if (IS_SVR_REV(svr, 1, 0))
328 puts("Work-around for Erratum A-008044 enabled\n");
329 #endif
330 #if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && \
331 (defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS))
332 puts("Work-around for Erratum XFI on B4860QDS enabled\n");
333 #endif
334 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
335 puts("Work-around for Erratum A009663 enabled\n");
336 #endif
337 #ifdef CONFIG_SYS_FSL_ERRATUM_A007907
338 puts("Work-around for Erratum A007907 enabled\n");
339 #endif
340 #ifdef CONFIG_SYS_FSL_ERRATUM_A007815
341 puts("Work-around for Erratum A007815 enabled\n");
342 #endif
343
344 return 0;
345 }
346
347 U_BOOT_CMD(
348 errata, 1, 0, do_errata,
349 "Report errata workarounds",
350 ""
351 );
352