1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2002, 2003 Motorola Inc.
5 * Xianghua Xiao (X.Xiao@motorola.com)
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 */
10
11 #include <config.h>
12 #include <cpu_func.h>
13 #include <clock_legacy.h>
14 #include <display_options.h>
15 #include <init.h>
16 #include <irq_func.h>
17 #include <log.h>
18 #include <time.h>
19 #include <vsprintf.h>
20 #include <watchdog.h>
21 #include <command.h>
22 #include <fsl_esdhc.h>
23 #include <asm/cache.h>
24 #include <asm/global_data.h>
25 #include <asm/io.h>
26 #include <asm/mmu.h>
27 #include <fsl_ifc.h>
28 #include <asm/fsl_law.h>
29 #include <asm/fsl_lbc.h>
30 #include <post.h>
31 #include <asm/processor.h>
32 #include <fsl_ddr_sdram.h>
33 #include <asm/ppc.h>
34 #include <linux/delay.h>
35
36 DECLARE_GLOBAL_DATA_PTR;
37
38 /*
39 * Default board reset function
40 */
41 static void
__board_reset(void)42 __board_reset(void)
43 {
44 /* Do nothing */
45 }
46 void board_reset_prepare(void) __attribute__((weak, alias("__board_reset")));
47 void board_reset(void) __attribute__((weak, alias("__board_reset")));
48 void board_reset_last(void) __attribute__((weak, alias("__board_reset")));
49
checkcpu(void)50 int checkcpu (void)
51 {
52 sys_info_t sysinfo;
53 uint pvr, svr;
54 uint ver;
55 uint major, minor;
56 struct cpu_type *cpu;
57 char buf1[32], buf2[32];
58 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \
59 defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
60 ccsr_gur_t __iomem *gur =
61 (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
62 #endif
63
64 /*
65 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
66 * mode. Previous platform use ddr ratio to do the same. This
67 * information is only for display here.
68 */
69 #ifdef CONFIG_FSL_CORENET
70 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
71 u32 ddr_sync = 0; /* only async mode is supported */
72 #else
73 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
74 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
75 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
76 #else /* CONFIG_FSL_CORENET */
77 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
78 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
79 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
80 #else
81 u32 ddr_ratio = 0;
82 #endif /* CONFIG_DYNAMIC_DDR_CLK_FREQ || CONFIG_STATIC_DDR_CLK_FREQ */
83 #endif /* CONFIG_FSL_CORENET */
84
85 unsigned int i, core, nr_cores = cpu_numcores();
86 u32 mask = cpu_mask();
87
88 #ifdef CONFIG_HETROGENOUS_CLUSTERS
89 unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
90 u32 dsp_mask = cpu_dsp_mask();
91 #endif
92
93 svr = get_svr();
94 major = SVR_MAJ(svr);
95 minor = SVR_MIN(svr);
96
97 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
98 if (SVR_SOC_VER(svr) == SVR_T4080) {
99 ccsr_rcpm_t *rcpm =
100 (void __iomem *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
101
102 setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
103 FSL_CORENET_DEVDISR2_DTSEC1_9);
104 setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
105 setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
106
107 /* It needs SW to disable core4~7 as HW design sake on T4080 */
108 for (i = 4; i < 8; i++)
109 cpu_disable(i);
110
111 /* request core4~7 into PH20 state, prior to entering PCL10
112 * state, all cores in cluster should be placed in PH20 state.
113 */
114 setbits_be32(&rcpm->pcph20setr, 0xf0);
115
116 /* put the 2nd cluster into PCL10 state */
117 setbits_be32(&rcpm->clpcl10setr, 1 << 1);
118 }
119 #endif
120
121 if (cpu_numcores() > 1) {
122 #ifndef CONFIG_MP
123 puts("Unicore software on multiprocessor system!!\n"
124 "To enable mutlticore build define CONFIG_MP\n");
125 #endif
126 volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
127 printf("CPU%d: ", pic->whoami);
128 } else {
129 puts("CPU: ");
130 }
131
132 cpu = gd->arch.cpu;
133
134 puts(cpu->name);
135 if (IS_E_PROCESSOR(svr))
136 puts("E");
137
138 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
139
140 pvr = get_pvr();
141 ver = PVR_VER(pvr);
142 major = PVR_MAJ(pvr);
143 minor = PVR_MIN(pvr);
144
145 printf("Core: ");
146 switch(ver) {
147 case PVR_VER_E500_V1:
148 puts("e500v1");
149 break;
150 case PVR_VER_E500_V2:
151 puts("e500v2");
152 break;
153 case PVR_VER_E500MC:
154 puts("e500mc");
155 break;
156 case PVR_VER_E5500:
157 puts("e5500");
158 break;
159 case PVR_VER_E6500:
160 puts("e6500");
161 break;
162 default:
163 puts("Unknown");
164 break;
165 }
166
167 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
168
169 if (nr_cores > CONFIG_MAX_CPUS) {
170 panic("\nUnexpected number of cores: %d, max is %d\n",
171 nr_cores, CONFIG_MAX_CPUS);
172 }
173
174 get_sys_info(&sysinfo);
175
176 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
177 if (sysinfo.diff_sysclk == 1)
178 puts("Single Source Clock Configuration\n");
179 #endif
180
181 puts("Clock Configuration:");
182 for_each_cpu(i, core, nr_cores, mask) {
183 if (!(i & 3))
184 printf ("\n ");
185 printf("CPU%d:%-4s MHz, ", core,
186 strmhz(buf1, sysinfo.freq_processor[core]));
187 }
188
189 #ifdef CONFIG_HETROGENOUS_CLUSTERS
190 for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
191 if (!(j & 3))
192 printf("\n ");
193 printf("DSP CPU%d:%-4s MHz, ", j,
194 strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
195 }
196 #endif
197
198 printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
199 printf("\n");
200
201 #ifdef CONFIG_FSL_CORENET
202 if (ddr_sync == 1) {
203 printf(" DDR:%-4s MHz (%s MT/s data rate) "
204 "(Synchronous), ",
205 strmhz(buf1, sysinfo.freq_ddrbus/2),
206 strmhz(buf2, sysinfo.freq_ddrbus));
207 } else {
208 printf(" DDR:%-4s MHz (%s MT/s data rate) "
209 "(Asynchronous), ",
210 strmhz(buf1, sysinfo.freq_ddrbus/2),
211 strmhz(buf2, sysinfo.freq_ddrbus));
212 }
213 #else
214 switch (ddr_ratio) {
215 case 0x0:
216 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
217 strmhz(buf1, sysinfo.freq_ddrbus/2),
218 strmhz(buf2, sysinfo.freq_ddrbus));
219 break;
220 case 0x7:
221 printf(" DDR:%-4s MHz (%s MT/s data rate) "
222 "(Synchronous), ",
223 strmhz(buf1, sysinfo.freq_ddrbus/2),
224 strmhz(buf2, sysinfo.freq_ddrbus));
225 break;
226 default:
227 printf(" DDR:%-4s MHz (%s MT/s data rate) "
228 "(Asynchronous), ",
229 strmhz(buf1, sysinfo.freq_ddrbus/2),
230 strmhz(buf2, sysinfo.freq_ddrbus));
231 break;
232 }
233 #endif
234
235 #if defined(CONFIG_FSL_LBC)
236 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
237 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
238 } else {
239 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
240 sysinfo.freq_localbus);
241 }
242 #endif
243
244 #if defined(CONFIG_FSL_IFC)
245 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
246 #endif
247
248 #ifdef CONFIG_QE
249 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
250 #endif
251
252 #if defined(CONFIG_SYS_CPRI)
253 printf(" ");
254 printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
255 #endif
256
257 #if defined(CONFIG_SYS_MAPLE)
258 printf("\n ");
259 printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
260 printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
261 printf("MAPLE-eTVPE:%-4s MHz\n",
262 strmhz(buf1, sysinfo.freq_maple_etvpe));
263 #endif
264
265 #ifdef CONFIG_SYS_DPAA_FMAN
266 for (i = 0; i < CFG_SYS_NUM_FMAN; i++) {
267 printf(" FMAN%d: %s MHz\n", i + 1,
268 strmhz(buf1, sysinfo.freq_fman[i]));
269 }
270 #endif
271
272 #ifdef CONFIG_SYS_DPAA_QBMAN
273 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
274 #endif
275
276 #ifdef CONFIG_SYS_DPAA_PME
277 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
278 #endif
279
280 puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
281
282 #ifdef CONFIG_FSL_CORENET
283 /* Display the RCW, so that no one gets confused as to what RCW
284 * we're actually using for this boot.
285 */
286 puts("Reset Configuration Word (RCW):");
287 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
288 u32 rcw = in_be32(&gur->rcwsr[i]);
289
290 if ((i % 4) == 0)
291 printf("\n %08x:", i * 4);
292 printf(" %08x", rcw);
293 }
294 puts("\n");
295 #endif
296
297 return 0;
298 }
299
300 /* ------------------------------------------------------------------------- */
301
do_reset(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])302 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
303 {
304 /* Everything after the first generation of PQ3 parts has RSTCR */
305 #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560)
306 unsigned long val, msr;
307
308 /*
309 * Initiate hard reset in debug control register DBCR0
310 * Make sure MSR[DE] = 1. This only resets the core.
311 */
312 msr = mfmsr ();
313 msr |= MSR_DE;
314 mtmsr (msr);
315
316 val = mfspr(DBCR0);
317 val |= 0x70000000;
318 mtspr(DBCR0,val);
319 #else
320 volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
321
322 /* Call board-specific preparation for reset */
323 board_reset_prepare();
324
325 /* Attempt board-specific reset */
326 board_reset();
327
328 /* Next try asserting HRESET_REQ */
329 out_be32(&gur->rstcr, 0x2);
330 udelay(100);
331
332 /* Attempt last-stage board-specific reset */
333 board_reset_last();
334 #endif
335
336 return 1;
337 }
338
339 /*
340 * Get timebase clock frequency
341 */
get_tbclk(void)342 __weak unsigned long get_tbclk(void)
343 {
344 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
345
346 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
347 }
348
349 /*
350 * Initializes on-chip MMC controllers.
351 * to override, implement board_mmc_init()
352 */
cpu_mmc_init(struct bd_info * bis)353 int cpu_mmc_init(struct bd_info *bis)
354 {
355 #ifdef CONFIG_FSL_ESDHC
356 return fsl_esdhc_mmc_init(bis);
357 #else
358 return 0;
359 #endif
360 }
361
362 /*
363 * Print out the state of various machine registers.
364 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
365 * parameters for IFC and TLBs
366 */
print_reginfo(void)367 void print_reginfo(void)
368 {
369 print_tlbcam();
370 #ifdef CONFIG_FSL_LAW
371 print_laws();
372 #endif
373 #if defined(CONFIG_FSL_LBC)
374 print_lbc_regs();
375 #endif
376 #ifdef CONFIG_FSL_IFC
377 print_ifc_regs();
378 #endif
379
380 }
381
382 /* Common ddr init for non-corenet fsl 85xx platforms */
383 #ifndef CONFIG_FSL_CORENET
384 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
385 !defined(CFG_SYS_INIT_L2_ADDR)
dram_init(void)386 int dram_init(void)
387 {
388 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
389 defined(CONFIG_ARCH_QEMU_E500)
390 gd->ram_size = fsl_ddr_sdram_size();
391 #else
392 gd->ram_size = (phys_size_t)CFG_SYS_SDRAM_SIZE * 1024 * 1024;
393 #endif
394
395 return 0;
396 }
397 #else /* CONFIG_SYS_RAMBOOT */
dram_init(void)398 int dram_init(void)
399 {
400 phys_size_t dram_size = 0;
401
402 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
403 {
404 ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
405 unsigned int x = 10;
406 unsigned int i;
407
408 /*
409 * Work around to stabilize DDR DLL
410 */
411 out_be32(&gur->ddrdllcr, 0x81000000);
412 asm("sync;isync;msync");
413 udelay(200);
414 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
415 setbits_be32(&gur->devdisr, 0x00010000);
416 for (i = 0; i < x; i++)
417 ;
418 clrbits_be32(&gur->devdisr, 0x00010000);
419 x++;
420 }
421 }
422 #endif
423
424 #if defined(CONFIG_SPD_EEPROM) || \
425 defined(CONFIG_DDR_SPD) || \
426 defined(CONFIG_SYS_DDR_RAW_TIMING)
427 dram_size = fsl_ddr_sdram();
428 #else
429 dram_size = fixed_sdram();
430 #endif
431 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
432 dram_size *= 0x100000;
433
434 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
435 /*
436 * Initialize and enable DDR ECC.
437 */
438 ddr_enable_ecc(dram_size);
439 #endif
440
441 #if defined(CONFIG_FSL_LBC)
442 /* Some boards also have sdram on the lbc */
443 lbc_sdram_init();
444 #endif
445
446 debug("DDR: ");
447 gd->ram_size = dram_size;
448
449 return 0;
450 }
451 #endif /* CONFIG_SYS_RAMBOOT */
452 #endif
453
454 #if CFG_POST & CFG_SYS_POST_MEMORY
455
456 /* Board-specific functions defined in each board's ddr.c */
457 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
458 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
459 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
460 phys_addr_t *rpn);
461 unsigned int
462 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
463
464 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
465
dump_spd_ddr_reg(void)466 static void dump_spd_ddr_reg(void)
467 {
468 int i, j, k, m;
469 u8 *p_8;
470 u32 *p_32;
471 struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
472 generic_spd_eeprom_t
473 spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
474
475 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
476 fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
477
478 puts("SPD data of all dimms (zero value is omitted)...\n");
479 puts("Byte (hex) ");
480 k = 1;
481 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
482 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
483 printf("Dimm%d ", k++);
484 }
485 puts("\n");
486 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
487 m = 0;
488 printf("%3d (0x%02x) ", k, k);
489 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
490 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
491 p_8 = (u8 *) &spd[i][j];
492 if (p_8[k]) {
493 printf("0x%02x ", p_8[k]);
494 m++;
495 } else
496 puts(" ");
497 }
498 }
499 if (m)
500 puts("\n");
501 else
502 puts("\r");
503 }
504
505 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
506 switch (i) {
507 case 0:
508 ddr[i] = (void *)CFG_SYS_FSL_DDR_ADDR;
509 break;
510 #if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
511 case 1:
512 ddr[i] = (void *)CFG_SYS_FSL_DDR2_ADDR;
513 break;
514 #endif
515 #if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
516 case 2:
517 ddr[i] = (void *)CFG_SYS_FSL_DDR3_ADDR;
518 break;
519 #endif
520 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
521 case 3:
522 ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
523 break;
524 #endif
525 default:
526 printf("%s unexpected controller number = %u\n",
527 __func__, i);
528 return;
529 }
530 }
531 printf("DDR registers dump for all controllers "
532 "(zero value is omitted)...\n");
533 puts("Offset (hex) ");
534 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
535 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
536 puts("\n");
537 for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
538 m = 0;
539 printf("%6d (0x%04x)", k * 4, k * 4);
540 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
541 p_32 = (u32 *) ddr[i];
542 if (p_32[k]) {
543 printf(" 0x%08x", p_32[k]);
544 m++;
545 } else
546 puts(" ");
547 }
548 if (m)
549 puts("\n");
550 else
551 puts("\r");
552 }
553 puts("\n");
554 }
555
556 /* invalid the TLBs for DDR and setup new ones to cover p_addr */
reset_tlb(phys_addr_t p_addr,u32 size,phys_addr_t * phys_offset)557 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
558 {
559 u32 vstart = CFG_SYS_DDR_SDRAM_BASE;
560 unsigned long epn;
561 u32 tsize, valid, ptr;
562 int ddr_esel;
563
564 clear_ddr_tlbs_phys(p_addr, size>>20);
565
566 /* Setup new tlb to cover the physical address */
567 setup_ddr_tlbs_phys(p_addr, size>>20);
568
569 ptr = vstart;
570 ddr_esel = find_tlb_idx((void *)ptr, 1);
571 if (ddr_esel != -1) {
572 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
573 } else {
574 printf("TLB error in function %s\n", __func__);
575 return -1;
576 }
577
578 return 0;
579 }
580
581 /*
582 * slide the testing window up to test another area
583 * for 32_bit system, the maximum testable memory is limited to
584 * CFG_MAX_MEM_MAPPED
585 */
arch_memory_test_advance(u32 * vstart,u32 * size,phys_addr_t * phys_offset)586 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
587 {
588 phys_addr_t test_cap, p_addr;
589 phys_size_t p_size = min(gd->ram_size, CFG_MAX_MEM_MAPPED);
590
591 #if !defined(CONFIG_PHYS_64BIT) || \
592 !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \
593 (CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
594 test_cap = p_size;
595 #else
596 test_cap = gd->ram_size;
597 #endif
598 p_addr = (*vstart) + (*size) + (*phys_offset);
599 if (p_addr < test_cap - 1) {
600 p_size = min(test_cap - p_addr, CFG_MAX_MEM_MAPPED);
601 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
602 return -1;
603 *vstart = CFG_SYS_DDR_SDRAM_BASE;
604 *size = (u32) p_size;
605 printf("Testing 0x%08llx - 0x%08llx\n",
606 (u64)(*vstart) + (*phys_offset),
607 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
608 } else
609 return 1;
610
611 return 0;
612 }
613
614 /* initialization for testing area */
arch_memory_test_prepare(u32 * vstart,u32 * size,phys_addr_t * phys_offset)615 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
616 {
617 phys_size_t p_size = min(gd->ram_size, CFG_MAX_MEM_MAPPED);
618
619 *vstart = CFG_SYS_DDR_SDRAM_BASE;
620 *size = (u32) p_size; /* CFG_MAX_MEM_MAPPED < 4G */
621 *phys_offset = 0;
622
623 #if !defined(CONFIG_PHYS_64BIT) || \
624 !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \
625 (CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
626 if (gd->ram_size > CFG_MAX_MEM_MAPPED) {
627 puts("Cannot test more than ");
628 print_size(CFG_MAX_MEM_MAPPED,
629 " without proper 36BIT support.\n");
630 }
631 #endif
632 printf("Testing 0x%08llx - 0x%08llx\n",
633 (u64)(*vstart) + (*phys_offset),
634 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
635
636 return 0;
637 }
638
639 /* invalid TLBs for DDR and remap as normal after testing */
arch_memory_test_cleanup(u32 * vstart,u32 * size,phys_addr_t * phys_offset)640 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
641 {
642 unsigned long epn;
643 u32 tsize, valid, ptr;
644 phys_addr_t rpn = 0;
645 int ddr_esel;
646
647 /* disable the TLBs for this testing */
648 ptr = *vstart;
649
650 while (ptr < (*vstart) + (*size)) {
651 ddr_esel = find_tlb_idx((void *)ptr, 1);
652 if (ddr_esel != -1) {
653 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
654 disable_tlb(ddr_esel);
655 }
656 ptr += TSIZE_TO_BYTES(tsize);
657 }
658
659 puts("Remap DDR ");
660 setup_ddr_tlbs(gd->ram_size>>20);
661 puts("\n");
662
663 return 0;
664 }
665
arch_memory_failure_handle(void)666 void arch_memory_failure_handle(void)
667 {
668 dump_spd_ddr_reg();
669 }
670 #endif
671