1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000-2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 */
6
7 #include <init.h>
8 #include <watchdog.h>
9
10 #include <mpc8xx.h>
11 #include <asm/cpm_8xx.h>
12 #include <asm/io.h>
13
14 /*
15 * Breath some life into the CPU...
16 *
17 * Set up the memory map,
18 * initialize a bunch of registers,
19 * initialize the UPM's
20 */
cpu_init_f(immap_t __iomem * immr)21 void cpu_init_f(immap_t __iomem *immr)
22 {
23 memctl8xx_t __iomem *memctl = &immr->im_memctl;
24 ulong reg;
25
26 /* SYPCR - contains watchdog control (11-9) */
27
28 /* deactivate watchdog if not enabled in config */
29 if (!IS_ENABLED(CONFIG_WDT_MPC8xxx))
30 out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE);
31
32 schedule();
33
34 /* SIUMCR - contains debug pin configuration (11-6) */
35 setbits_be32(&immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR);
36 /* initialize timebase status and control register (11-26) */
37 /* unlock TBSCRK */
38
39 out_be32(&immr->im_sitk.sitk_tbscrk, KAPWR_KEY);
40 out_be16(&immr->im_sit.sit_tbscr, CONFIG_SYS_TBSCR | TBSCR_TBE);
41
42 /* Unlock timebase register */
43 out_be32(&immr->im_sitk.sitk_tbk, KAPWR_KEY);
44
45 /* initialize the PIT (11-31) */
46
47 out_be32(&immr->im_sitk.sitk_piscrk, KAPWR_KEY);
48 out_be16(&immr->im_sit.sit_piscr, CONFIG_SYS_PISCR);
49
50 /* System integration timers. Don't change EBDF! (15-27) */
51
52 out_be32(&immr->im_clkrstk.cark_sccrk, KAPWR_KEY);
53 clrsetbits_be32(&immr->im_clkrst.car_sccr, ~CONFIG_SYS_SCCR_MASK,
54 CONFIG_SYS_SCCR);
55
56 /*
57 * MPC866/885 ERRATA GLL2
58 * Description:
59 * In 1:2:1 mode, when HRESET is detected at the positive edge of
60 * EXTCLK, then there will be a loss of phase between
61 * EXTCLK and CLKOUT.
62 *
63 * Workaround:
64 * Reprogram the SCCR:
65 * 1. Write 1'b00 to SCCR[EBDF].
66 * 2. Write 1'b01 to SCCR[EBDF].
67 * 3. Rewrite the desired value to the PLPRCR register.
68 */
69 reg = in_be32(&immr->im_clkrst.car_sccr);
70 /* Are we in mode 1:2:1 ? */
71 if ((reg & SCCR_EBDF11) == SCCR_EBDF01) {
72 clrbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF11);
73 setbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF01);
74 }
75
76 /* PLL (CPU clock) settings (15-30) */
77
78 out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
79
80 /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
81 * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
82 * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF
83 * field value.
84 *
85 * For newer (starting MPC866) chips PLPRCR layout is different.
86 */
87 #ifdef CONFIG_SYS_PLPRCR
88 if ((CONFIG_SYS_PLPRCR & PLPRCR_MFACT_MSK) != 0) /* reset control bits*/
89 out_be32(&immr->im_clkrst.car_plprcr, CONFIG_SYS_PLPRCR);
90 else /* isolate MF-related fields and reset control bits */
91 clrsetbits_be32(&immr->im_clkrst.car_plprcr, ~PLPRCR_MFACT_MSK,
92 CONFIG_SYS_PLPRCR);
93 #endif
94
95 /* Set SDMA configuration register */
96 if (IS_ENABLED(CONFIG_MPC885))
97 out_be32(&immr->im_siu_conf.sc_sdcr, 0x0040);
98 else
99 out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001);
100
101 /*
102 * Memory Controller:
103 */
104
105 /* Clear everything except Port Size bits & add the "Bank Valid" bit */
106 clrsetbits_be32(&memctl->memc_br0, ~BR_PS_MSK, BR_V);
107
108 /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
109 * preliminary addresses - these have to be modified later
110 * when FLASH size has been determined
111 *
112 * Depending on the size of the memory region defined by
113 * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the
114 * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't
115 * map CONFIG_SYS_MONITOR_BASE.
116 *
117 * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is
118 * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000.
119 *
120 * If BR0 wasn't loaded with address base 0xff000000, then BR0's
121 * base address remains as 0x00000000. However, the address mask
122 * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped
123 * into the Bank0.
124 *
125 * This is why CONFIG_IVMS8 and similar boards must load BR0 with
126 * CONFIG_SYS_BR0_PRELIM in advance.
127 *
128 * [Thanks to Michael Liao for this explanation.
129 * I owe him a free beer. - wd]
130 */
131
132 #if defined(CONFIG_SYS_OR0_REMAP)
133 out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_REMAP);
134 #endif
135 #if defined(CONFIG_SYS_OR1_REMAP)
136 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_REMAP);
137 #endif
138 #if defined(CONFIG_SYS_OR5_REMAP)
139 out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_REMAP);
140 #endif
141
142 /* now restrict to preliminary range */
143 out_be32(&memctl->memc_br0, CONFIG_SYS_BR0_PRELIM);
144 out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_PRELIM);
145
146 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
147 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
148 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
149 #endif
150
151 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
152 out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_PRELIM);
153 out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_PRELIM);
154 #endif
155
156 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
157 out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_PRELIM);
158 out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_PRELIM);
159 #endif
160
161 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
162 out_be32(&memctl->memc_or4, CONFIG_SYS_OR4_PRELIM);
163 out_be32(&memctl->memc_br4, CONFIG_SYS_BR4_PRELIM);
164 #endif
165
166 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
167 out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_PRELIM);
168 out_be32(&memctl->memc_br5, CONFIG_SYS_BR5_PRELIM);
169 #endif
170
171 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
172 out_be32(&memctl->memc_or6, CONFIG_SYS_OR6_PRELIM);
173 out_be32(&memctl->memc_br6, CONFIG_SYS_BR6_PRELIM);
174 #endif
175
176 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
177 out_be32(&memctl->memc_or7, CONFIG_SYS_OR7_PRELIM);
178 out_be32(&memctl->memc_br7, CONFIG_SYS_BR7_PRELIM);
179 #endif
180
181 /*
182 * Reset CPM
183 */
184 out_be16(&immr->im_cpm.cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
185 /* Spin until command processed */
186 while (in_be16(&immr->im_cpm.cp_cpcr) & CPM_CR_FLG)
187 ;
188 }
189
190 /*
191 * initialize higher level parts of CPU like timers
192 */
cpu_init_r(void)193 int cpu_init_r(void)
194 {
195 return 0;
196 }
197