1 #ifndef _PPC_KERNEL_MPC8349_PCI_H 2 #define _PPC_KERNEL_MPC8349_PCI_H 3 4 #define M8265_PCIBR0 0x101ac 5 #define M8265_PCIBR1 0x101b0 6 #define M8265_PCIMSK0 0x101c4 7 #define M8265_PCIMSK1 0x101c8 8 9 /* Bit definitions for PCIBR registers */ 10 11 #define PCIBR_ENABLE 0x00000001 12 13 /* Bit definitions for PCIMSK registers */ 14 15 #define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */ 16 #define PCIMSK_64KB 0xFFFF0000 17 #define PCIMSK_128KB 0xFFFE0000 18 #define PCIMSK_256KB 0xFFFC0000 19 #define PCIMSK_512KB 0xFFF80000 20 #define PCIMSK_1MB 0xFFF00000 21 #define PCIMSK_2MB 0xFFE00000 22 #define PCIMSK_4MB 0xFFC00000 23 #define PCIMSK_8MB 0xFF800000 24 #define PCIMSK_16MB 0xFF000000 25 #define PCIMSK_32MB 0xFE000000 26 #define PCIMSK_64MB 0xFC000000 27 #define PCIMSK_128MB 0xF8000000 28 #define PCIMSK_256MB 0xF0000000 29 #define PCIMSK_512MB 0xE0000000 30 #define PCIMSK_1GB 0xC0000000 /* Size of window, largest */ 31 32 #define M826X_SCCR_PCI_MODE_EN 0x100 33 34 /* 35 * Outbound ATU registers (3 sets). These registers control how 60x bus 36 * (local) addresses are translated to PCI addresses when the MPC826x is 37 * a PCI bus master (initiator). 38 */ 39 40 #define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */ 41 #define POTAR_REG1 0x10818 42 #define POTAR_REG2 0x10830 43 44 #define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */ 45 #define POBAR_REG1 0x10820 46 #define POBAR_REG2 0x10838 47 48 #define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */ 49 #define POCMR_REG1 0x10828 50 #define POCMR_REG2 0x10840 51 52 /* Bit definitions for POMCR registers */ 53 54 #define POCMR_MASK_4KB 0x000FFFFF 55 #define POCMR_MASK_8KB 0x000FFFFE 56 #define POCMR_MASK_16KB 0x000FFFFC 57 #define POCMR_MASK_32KB 0x000FFFF8 58 #define POCMR_MASK_64KB 0x000FFFF0 59 #define POCMR_MASK_128KB 0x000FFFE0 60 #define POCMR_MASK_256KB 0x000FFFC0 61 #define POCMR_MASK_512KB 0x000FFF80 62 #define POCMR_MASK_1MB 0x000FFF00 63 #define POCMR_MASK_2MB 0x000FFE00 64 #define POCMR_MASK_4MB 0x000FFC00 65 #define POCMR_MASK_8MB 0x000FF800 66 #define POCMR_MASK_16MB 0x000FF000 67 #define POCMR_MASK_32MB 0x000FE000 68 #define POCMR_MASK_64MB 0x000FC000 69 #define POCMR_MASK_128MB 0x000F8000 70 #define POCMR_MASK_256MB 0x000F0000 71 #define POCMR_MASK_512MB 0x000E0000 72 #define POCMR_MASK_1GB 0x000C0000 73 74 #define POCMR_ENABLE 0x80000000 75 #define POCMR_PCI_IO 0x40000000 76 #define POCMR_PREFETCH_EN 0x20000000 77 #define POCMR_PCI2 0x10000000 78 79 /* Soft PCI reset */ 80 81 #define PCI_GCR_REG 0x10880 82 83 /* Bit definitions for PCI_GCR registers */ 84 85 #define PCIGCR_PCI_BUS_EN 0x1 86 87 /* 88 * Inbound ATU registers (2 sets). These registers control how PCI 89 * addresses are translated to 60x bus (local) addresses when the 90 * MPC826x is a PCI bus target. 91 */ 92 93 #define PITAR_REG1 0x108D0 94 #define PIBAR_REG1 0x108D8 95 #define PICMR_REG1 0x108E0 96 #define PITAR_REG0 0x108E8 97 #define PIBAR_REG0 0x108F0 98 #define PICMR_REG0 0x108F8 99 100 /* Bit definitions for PCI Inbound Comparison Mask registers */ 101 102 #define PICMR_MASK_4KB 0x000FFFFF 103 #define PICMR_MASK_8KB 0x000FFFFE 104 #define PICMR_MASK_16KB 0x000FFFFC 105 #define PICMR_MASK_32KB 0x000FFFF8 106 #define PICMR_MASK_64KB 0x000FFFF0 107 #define PICMR_MASK_128KB 0x000FFFE0 108 #define PICMR_MASK_256KB 0x000FFFC0 109 #define PICMR_MASK_512KB 0x000FFF80 110 #define PICMR_MASK_1MB 0x000FFF00 111 #define PICMR_MASK_2MB 0x000FFE00 112 #define PICMR_MASK_4MB 0x000FFC00 113 #define PICMR_MASK_8MB 0x000FF800 114 #define PICMR_MASK_16MB 0x000FF000 115 #define PICMR_MASK_32MB 0x000FE000 116 #define PICMR_MASK_64MB 0x000FC000 117 #define PICMR_MASK_128MB 0x000F8000 118 #define PICMR_MASK_256MB 0x000F0000 119 #define PICMR_MASK_512MB 0x000E0000 120 #define PICMR_MASK_1GB 0x000C0000 121 122 #define PICMR_ENABLE 0x80000000 123 #define PICMR_NO_SNOOP_EN 0x40000000 124 #define PICMR_PREFETCH_EN 0x20000000 125 126 /* PCI error Registers */ 127 128 #define PCI_ERROR_STATUS_REG 0x10884 129 #define PCI_ERROR_MASK_REG 0x10888 130 #define PCI_ERROR_CONTROL_REG 0x1088C 131 #define PCI_ERROR_ADRS_CAPTURE_REG 0x10890 132 #define PCI_ERROR_DATA_CAPTURE_REG 0x10898 133 #define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0 134 135 /* PCI error Register bit defines */ 136 137 #define PCI_ERROR_PCI_ADDR_PAR 0x00000001 138 #define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002 139 #define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004 140 #define PCI_ERROR_PCI_NO_RSP 0x00000008 141 #define PCI_ERROR_PCI_TAR_ABT 0x00000010 142 #define PCI_ERROR_PCI_SERR 0x00000020 143 #define PCI_ERROR_PCI_PERR_RD 0x00000040 144 #define PCI_ERROR_PCI_PERR_WR 0x00000080 145 #define PCI_ERROR_I2O_OFQO 0x00000100 146 #define PCI_ERROR_I2O_IPQO 0x00000200 147 #define PCI_ERROR_IRA 0x00000400 148 #define PCI_ERROR_NMI 0x00000800 149 #define PCI_ERROR_I2O_DBMC 0x00001000 150 151 /* 152 * Register pair used to generate configuration cycles on the PCI bus 153 * and access the MPC826x's own PCI configuration registers. 154 */ 155 156 #define PCI_CFG_ADDR_REG 0x10900 157 #define PCI_CFG_DATA_REG 0x10904 158 159 /* Bus parking decides where the bus control sits when idle */ 160 /* If modifying memory controllers for PCI park on the core */ 161 162 #define PPC_ACR_BUS_PARK_CORE 0x6 163 #define PPC_ACR_BUS_PARK_PCI 0x3 164 165 #endif /* _PPC_KERNEL_M8260_PCI_H */ 166