1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
4 */
5 #include <asm/arch/iopmp.h>
6 #include <asm/io.h>
7 #include <cpu_func.h>
8 #include <dm.h>
9 #include <linux/sizes.h>
10 #include <log.h>
11 #include <init.h>
12
13 DECLARE_GLOBAL_DATA_PTR;
14
15 #define TH1520_SUBSYS_CLK (void __iomem *)(0xffff011000 + 0x220)
16 #define TH1520_SUBSYS_CLK_VO_EN BIT(2)
17 #define TH1520_SUBSYS_CLK_VI_EN BIT(1)
18 #define TH1520_SUBSYS_CLK_DSP_EN BIT(0)
19 #define TH1520_SUBSYS_RST (void __iomem *)(0xffff015000 + 0x220)
20 #define TH1520_SUBSYS_RST_VP_N BIT(3)
21 #define TH1520_SUBSYS_RST_VO_N BIT(2)
22 #define TH1520_SUBSYS_RST_VI_N BIT(1)
23 #define TH1520_SUBSYS_RST_DSP_N BIT(0)
24
25 #define CSR_MXSTATUS 0x7c0
26 #define CSR_MXSTATUS_THEADISAEE BIT(22)
27 #define CSR_MXSTATUS_MAEE BIT(21)
28 #define CSR_MXSTATUS_CLINTEE BIT(17)
29 #define CSR_MXSTATUS_UCME BIT(16)
30 #define CSR_MXSTATUS_MM BIT(15)
31 #define CSR_MHCR 0x7c1
32 #define CSR_MHCR_WBR BIT(8)
33 #define CSR_MHCR_BTB BIT(6)
34 #define CSR_MHCR_BPE BIT(5)
35 #define CSR_MHCR_RS BIT(4)
36 #define CSR_MHCR_WB BIT(3)
37 #define CSR_MHCR_WA BIT(2)
38 #define CSR_MHCR_DE BIT(1)
39 #define CSR_MHCR_IE BIT(0)
40 #define CSR_MCOR 0x7c2
41 #define CSR_MCOR_IBP_INV BIT(18)
42 #define CSR_MCOR_BTB_INV BIT(17)
43 #define CSR_MCOR_BHT_INV BIT(16)
44 #define CSR_MCOR_CACHE_INV BIT(4)
45 #define CSR_MCCR2 0x7c3
46 #define CSR_MCCR2_TPRF BIT(31)
47 #define CSR_MCCR2_IPRF(n) ((n) << 29)
48 #define CSR_MCCR2_TSETUP BIT(25)
49 #define CSR_MCCR2_TLNTCY(n) ((n) << 22)
50 #define CSR_MCCR2_DSETUP BIT(19)
51 #define CSR_MCCR2_DLNTCY(n) ((n) << 16)
52 #define CSR_MCCR2_L2EN BIT(3)
53 #define CSR_MCCR2_RFE BIT(0)
54 #define CSR_MHINT 0x7c5
55 #define CSR_MHINT_FENCERW_BROAD_DIS BIT(22)
56 #define CSR_MHINT_TLB_BRAOD_DIS BIT(21)
57 #define CSR_MHINT_NSFE BIT(18)
58 #define CSR_MHINT_L2_PREF_DIST(n) ((n) << 16)
59 #define CSR_MHINT_L2PLD BIT(15)
60 #define CSR_MHINT_DCACHE_PREF_DIST(n) ((n) << 13)
61 #define CSR_MHINT_LPE BIT(9)
62 #define CSR_MHINT_ICACHE_PREF BIT(8)
63 #define CSR_MHINT_AMR BIT(3)
64 #define CSR_MHINT_DCACHE_PREF BIT(2)
65 #define CSR_MHINT2 0x7cc
66 #define CSR_MHINT2_LOCAL_ICG_EN(n) BIT((n) + 14)
67 #define CSR_MHINT4 0x7ce
68 #define CSR_MSMPR 0x7f3
69 #define CSR_MSMPR_SMPEN BIT(0)
70
spl_dram_init(void)71 int spl_dram_init(void)
72 {
73 int ret;
74 struct udevice *dev;
75
76 ret = fdtdec_setup_mem_size_base();
77 if (ret) {
78 printf("failed to setup memory size and base: %d\n", ret);
79 return ret;
80 }
81
82 /* DDR init */
83 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
84 if (ret) {
85 printf("DRAM init failed: %d\n", ret);
86 return ret;
87 }
88
89 return 0;
90 }
91
92 static void __iomem *th1520_iopmp_regs[] = {
93 TH1520_IOPMP_EMMC,
94 TH1520_IOPMP_SDIO0,
95 TH1520_IOPMP_SDIO1,
96 TH1520_IOPMP_USB0,
97 TH1520_IOPMP_AO,
98 TH1520_IOPMP_AUD,
99 TH1520_IOPMP_CHIP_DBG,
100 TH1520_IOPMP_EIP120I,
101 TH1520_IOPMP_EIP120II,
102 TH1520_IOPMP_EIP120III,
103 TH1520_IOPMP_ISP0,
104 TH1520_IOPMP_ISP1,
105 TH1520_IOPMP_DW200,
106 TH1520_IOPMP_VIPRE,
107 TH1520_IOPMP_VENC,
108 TH1520_IOPMP_VDEC,
109 TH1520_IOPMP_G2D,
110 TH1520_IOPMP_FCE,
111 TH1520_IOPMP_NPU,
112 TH1520_IOPMP_DPU0,
113 TH1520_IOPMP_DPU1,
114 TH1520_IOPMP_GPU,
115 TH1520_IOPMP_GMAC1,
116 TH1520_IOPMP_GMAC2,
117 TH1520_IOPMP_DMAC,
118 TH1520_IOPMP_TEE_DMAC,
119 TH1520_IOPMP_DSP0,
120 TH1520_IOPMP_DSP1,
121 };
122
harts_early_init(void)123 void harts_early_init(void)
124 {
125 int i;
126
127 /* Invalidate cache and buffer entries */
128 csr_write(CSR_MCOR, CSR_MCOR_IBP_INV | CSR_MCOR_BTB_INV |
129 CSR_MCOR_BHT_INV | CSR_MCOR_CACHE_INV | 0x3);
130
131 /* Enable cache snooping */
132 csr_write(CSR_MSMPR, CSR_MSMPR_SMPEN);
133
134 /*
135 * Configure and enable L2 cache,
136 * Enable tag/data RAM prefetch, both cost 2 cycles
137 * Prefetch 3 cache lines of instructions
138 * Enable read allocation
139 */
140 csr_write(CSR_MCCR2, CSR_MCCR2_TPRF | CSR_MCCR2_IPRF(3) |
141 CSR_MCCR2_TSETUP | CSR_MCCR2_TLNTCY(1) |
142 CSR_MCCR2_DSETUP | CSR_MCCR2_DLNTCY(1) |
143 CSR_MCCR2_L2EN | CSR_MCCR2_RFE);
144 csr_write(CSR_MXSTATUS, CSR_MXSTATUS_THEADISAEE | CSR_MXSTATUS_MAEE |
145 CSR_MXSTATUS_CLINTEE | CSR_MXSTATUS_UCME |
146 CSR_MXSTATUS_MM);
147 csr_write(CSR_MHINT, CSR_MHINT_FENCERW_BROAD_DIS |
148 CSR_MHINT_TLB_BRAOD_DIS |
149 CSR_MHINT_NSFE |
150 CSR_MHINT_L2_PREF_DIST(2) |
151 CSR_MHINT_L2PLD |
152 CSR_MHINT_DCACHE_PREF_DIST(3) |
153 CSR_MHINT_LPE |
154 CSR_MHINT_ICACHE_PREF |
155 CSR_MHINT_AMR |
156 CSR_MHINT_DCACHE_PREF);
157 csr_write(CSR_MHCR, CSR_MHCR_WBR | CSR_MHCR_BTB | CSR_MHCR_BPE |
158 CSR_MHCR_RS | CSR_MHCR_WB | CSR_MHCR_WA | 0x3);
159 csr_write(CSR_MHINT2, CSR_MHINT2_LOCAL_ICG_EN(8) |
160 CSR_MHINT2_LOCAL_ICG_EN(3));
161 csr_write(CSR_MHINT4, 0x410);
162
163 /*
164 * Set IOPMPs to the default attribute, allowing the application
165 * processor to access various peripherals. Subsystem clocks should be
166 * enabled and resets should be deasserted ahead of time, or the HART
167 * will hang when configuring corresponding IOPMP entries.
168 */
169 setbits_le32(TH1520_SUBSYS_CLK, TH1520_SUBSYS_CLK_VO_EN |
170 TH1520_SUBSYS_CLK_VI_EN |
171 TH1520_SUBSYS_CLK_DSP_EN);
172 setbits_le32(TH1520_SUBSYS_RST, TH1520_SUBSYS_RST_VP_N |
173 TH1520_SUBSYS_RST_VO_N |
174 TH1520_SUBSYS_RST_VI_N |
175 TH1520_SUBSYS_RST_DSP_N);
176
177 for (i = 0; i < ARRAY_SIZE(th1520_iopmp_regs); i++)
178 writel(TH1520_IOPMP_DEFAULT_ATTR, th1520_iopmp_regs[i]);
179 }
180