1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2011 Renesas Solutions Corp. 4 */ 5 6 #ifndef _ASM_CPU_SH7757_H_ 7 #define _ASM_CPU_SH7757_H_ 8 9 #define CCR 0xFF00001C 10 #define WTCNT 0xFFCC0000 11 #define CCR_CACHE_INIT 0x0000090b 12 #define CACHE_OC_NUM_WAYS 1 13 14 #ifndef __ASSEMBLY__ /* put C only stuff in this section */ 15 /* MMU */ 16 struct mmu_regs { 17 unsigned int reserved[4]; 18 unsigned int mmucr; 19 }; 20 #define MMU_BASE ((struct mmu_regs *)0xff000000) 21 22 /* Watchdog */ 23 #define WTCSR0 0xffcc0002 24 #define WRSTCSR_R 0xffcc0003 25 #define WRSTCSR_W 0xffcc0002 26 #define WTCSR_PREFIX 0xa500 27 #define WRSTCSR_PREFIX 0x6900 28 #define WRSTCSR_WOVF_PREFIX 0x9600 29 30 /* SCIF */ 31 #define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */ 32 #define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */ 33 #define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */ 34 35 /* SerMux */ 36 #define SMR0 0xfe470000 37 38 /* TMU0 */ 39 #define TMU_BASE 0xFE430000 40 41 /* ETHER, GETHER MAC address */ 42 struct ether_mac_regs { 43 unsigned int reserved[114]; 44 unsigned int mahr; 45 unsigned int reserved2; 46 unsigned int malr; 47 }; 48 #define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400) 49 #define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00) 50 #define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000) 51 #define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800) 52 53 /* GETHER */ 54 struct gether_control_regs { 55 unsigned int gbecont; 56 }; 57 #define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100) 58 #define GBECONT_RMII1 0x00020000 59 #define GBECONT_RMII0 0x00010000 60 61 /* USB0/1 */ 62 struct usb_common_regs { 63 unsigned short reserved[129]; 64 unsigned short suspmode; 65 }; 66 #define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000) 67 #define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000) 68 69 struct usb0_phy_regs { 70 unsigned short reset; 71 unsigned short reserved[4]; 72 unsigned short portsel; 73 }; 74 #define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000) 75 76 struct usb1_port_regs { 77 unsigned int port1sel; 78 unsigned int reserved; 79 unsigned int usb1intsts; 80 }; 81 #define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000) 82 83 struct usb1_alignment_regs { 84 unsigned int ehcidatac; /* 0xfe4fe018 */ 85 unsigned int reserved[63]; 86 unsigned int ohcidatac; 87 }; 88 #define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018) 89 90 /* GCTRL, GRA */ 91 struct gctrl_regs { 92 unsigned int wprotect; 93 unsigned int gplldiv; 94 unsigned int gracr2; /* GRA */ 95 unsigned int gracr3; /* GRA */ 96 unsigned int reserved[4]; 97 unsigned int fcntcr1; 98 unsigned int fcntcr2; 99 unsigned int reserved2[2]; 100 unsigned int gpll1div; 101 unsigned int vcompsel; 102 unsigned int reserved3[62]; 103 unsigned int fdlmon; 104 unsigned int reserved4[2]; 105 unsigned int flcrmon; 106 unsigned int reserved5[944]; 107 unsigned int spibootcan; 108 }; 109 #define GCTRL_BASE ((struct gctrl_regs *)0xffc10000) 110 111 /* PCIe setup */ 112 struct pcie_setup_regs { 113 unsigned int pbictl0; 114 unsigned int gradevctl; 115 unsigned int reserved[2]; 116 unsigned int bmcinf[6]; 117 unsigned int reserved2[118]; 118 unsigned int idset[2]; 119 unsigned int subidset; 120 unsigned int reserved3[2]; 121 unsigned int linkconfset[4]; 122 unsigned int trsid; 123 unsigned int reserved4[6]; 124 unsigned int toutset; 125 unsigned int reserved5[7]; 126 unsigned int lad0; 127 unsigned int ladmsk0; 128 unsigned int lad1; 129 unsigned int ladmsk1; 130 unsigned int lad2; 131 unsigned int ladmsk2; 132 unsigned int lad3; 133 unsigned int ladmsk3; 134 unsigned int lad4; 135 unsigned int ladmsk4; 136 unsigned int lad5; 137 unsigned int ladmsk5; 138 unsigned int reserved6[94]; 139 unsigned int vdmrxvid[2]; 140 unsigned int reserved7; 141 unsigned int pbiintfr; 142 unsigned int pbiinten; 143 unsigned int msimap; 144 unsigned int barmap; 145 unsigned int baracsize; 146 unsigned int advserest; 147 unsigned int pbictl3; 148 unsigned int reserved8[8]; 149 unsigned int pbictl1; 150 unsigned int scratch0; 151 unsigned int reserved9[6]; 152 unsigned int pbictl2; 153 unsigned int reserved10; 154 unsigned int pbirev; 155 }; 156 #define PCIE_SETUP_BASE ((struct pcie_setup_regs *)0xffca1000) 157 158 struct pcie_system_bus_regs { 159 unsigned int reserved[3]; 160 unsigned int endictl0; 161 unsigned int endictl1; 162 }; 163 #define PCIE_SYSTEM_BUS_BASE ((struct pcie_system_bus_regs *)0xffca1600) 164 165 /* PCIe-Bridge */ 166 struct pciebrg_regs { 167 unsigned short ctrl_h8s; 168 unsigned short reserved[7]; 169 unsigned short cp_addr; 170 unsigned short reserved2; 171 unsigned short cp_data; 172 unsigned short reserved3; 173 unsigned short cp_ctrl; 174 }; 175 #define PCIEBRG_BASE ((struct pciebrg_regs *)0xffd60000) 176 177 /* CPU version */ 178 #define CCN_PRR 0xff000044 179 #define prr_mask(_val) ((_val >> 4) & 0xff) 180 #define PRR_SH7757_B0 0x10 181 #define PRR_SH7757_C0 0x11 182 183 #define is_sh7757_b0(_val) \ 184 ({ \ 185 int __ret = prr_mask(__raw_readl(CCN_PRR)) == PRR_SH7757_B0; \ 186 __ret; \ 187 }) 188 #endif /* ifndef __ASSEMBLY__ */ 189 190 #endif /* _ASM_CPU_SH7757_H_ */ 191