1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2019 Google LLC
4 *
5 * From coreboot Apollo Lake support lpc.c
6 */
7
8 #include <dm.h>
9 #include <log.h>
10 #include <spl.h>
11 #include <acpi/acpi_table.h>
12 #include <asm/cpu_common.h>
13 #include <asm/intel_acpi.h>
14 #include <asm/lpc_common.h>
15 #include <asm/pci.h>
16 #include <asm/arch/iomap.h>
17 #include <asm/arch/lpc.h>
18 #include <dm/acpi.h>
19 #include <linux/log2.h>
20
lpc_enable_fixed_io_ranges(uint io_enables)21 void lpc_enable_fixed_io_ranges(uint io_enables)
22 {
23 pci_x86_clrset_config(PCH_DEV_LPC, LPC_IO_ENABLES, 0, io_enables,
24 PCI_SIZE_16);
25 }
26
27 /*
28 * Find the first unused IO window.
29 * Returns -1 if not found, 0 for reg 0x84, 1 for reg 0x88 ...
30 */
find_unused_pmio_window(void)31 static int find_unused_pmio_window(void)
32 {
33 int i;
34 ulong lgir;
35
36 for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
37 pci_x86_read_config(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i),
38 &lgir, PCI_SIZE_32);
39
40 if (!(lgir & LPC_LGIR_EN))
41 return i;
42 }
43
44 return -1;
45 }
46
lpc_open_pmio_window(uint base,uint size)47 int lpc_open_pmio_window(uint base, uint size)
48 {
49 int i, lgir_reg_num;
50 u32 lgir_reg_offset, lgir, window_size, alignment;
51 ulong bridged_size, bridge_base;
52 ulong reg;
53
54 log_debug("LPC: Trying to open IO window from %x size %x\n", base,
55 size);
56
57 bridged_size = 0;
58 bridge_base = base;
59
60 while (bridged_size < size) {
61 /* Each IO range register can only open a 256-byte window */
62 window_size = min(size, (uint)LPC_LGIR_MAX_WINDOW_SIZE);
63
64 /* Window size must be a power of two for the AMASK to work */
65 alignment = 1UL << (order_base_2(window_size));
66 window_size = ALIGN(window_size, alignment);
67
68 /* Address[15:2] in LGIR[15:12] and Mask[7:2] in LGIR[23:18] */
69 lgir = (bridge_base & LPC_LGIR_ADDR_MASK) | LPC_LGIR_EN;
70 lgir |= ((window_size - 1) << 16) & LPC_LGIR_AMASK_MASK;
71
72 /* Skip programming if same range already programmed */
73 for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
74 pci_x86_read_config(PCH_DEV_LPC,
75 LPC_GENERIC_IO_RANGE(i), ®,
76 PCI_SIZE_32);
77 if (lgir == reg)
78 return -EALREADY;
79 }
80
81 lgir_reg_num = find_unused_pmio_window();
82 if (lgir_reg_num < 0) {
83 if (xpl_phase() > PHASE_TPL) {
84 log_err("LPC: Cannot open IO window: %lx size %lx\n",
85 bridge_base, size - bridged_size);
86 log_err("No more IO windows\n");
87 }
88 return -ENOSPC;
89 }
90 lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num);
91
92 pci_x86_write_config(PCH_DEV_LPC, lgir_reg_offset, lgir,
93 PCI_SIZE_32);
94
95 log_debug("LPC: Opened IO window LGIR%d: base %lx size %x\n",
96 lgir_reg_num, bridge_base, window_size);
97
98 bridged_size += window_size;
99 bridge_base += window_size;
100 }
101
102 return 0;
103 }
104
lpc_io_setup_comm_a_b(void)105 void lpc_io_setup_comm_a_b(void)
106 {
107 /* ComA Range 3F8h-3FFh [2:0] */
108 u16 com_ranges = LPC_IOD_COMA_RANGE;
109 u16 com_enable = LPC_IOE_COMA_EN;
110
111 /* Setup I/O Decode Range Register for LPC */
112 pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, com_ranges);
113 /* Enable ComA and ComB Port */
114 lpc_enable_fixed_io_ranges(com_enable);
115 }
116
apl_acpi_lpc_get_name(const struct udevice * dev,char * out_name)117 static int apl_acpi_lpc_get_name(const struct udevice *dev, char *out_name)
118 {
119 return acpi_copy_name(out_name, "LPCB");
120 }
121
122 struct acpi_ops apl_lpc_acpi_ops = {
123 .get_name = apl_acpi_lpc_get_name,
124 #ifdef CONFIG_GENERATE_ACPI_TABLE
125 .write_tables = intel_southbridge_write_acpi_tables,
126 #endif
127 .inject_dsdt = southbridge_inject_dsdt,
128 };
129
130 #if CONFIG_IS_ENABLED(OF_REAL)
131 static const struct udevice_id apl_lpc_ids[] = {
132 { .compatible = "intel,apl-lpc" },
133 { }
134 };
135 #endif
136
137 /* All pads are LPC already configured by the hostbridge, so no probing here */
138 U_BOOT_DRIVER(intel_apl_lpc) = {
139 .name = "intel_apl_lpc",
140 .id = UCLASS_LPC,
141 .of_match = of_match_ptr(apl_lpc_ids),
142 ACPI_OPS_PTR(&apl_lpc_acpi_ops)
143 };
144