1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Special driver to handle of-platdata
4 *
5 * Copyright 2019 Google LLC
6 *
7 * Some code from coreboot lpss.c
8 */
9
10 #include <dm.h>
11 #include <dt-structs.h>
12 #include <malloc.h>
13 #include <ns16550.h>
14 #include <spl.h>
15 #include <asm/io.h>
16 #include <asm/pci.h>
17 #include <asm/lpss.h>
18 #include <dm/device-internal.h>
19 #include <asm/arch/uart.h>
20
21 /* Low-power Subsystem (LPSS) clock register */
22 enum {
23 LPSS_CLOCK_CTL_REG = 0x200,
24 LPSS_CNT_CLOCK_EN = 1,
25 LPSS_CNT_CLK_UPDATE = 1U << 31,
26 LPSS_CLOCK_DIV_N_SHIFT = 16,
27 LPSS_CLOCK_DIV_N_MASK = 0x7fff << LPSS_CLOCK_DIV_N_SHIFT,
28 LPSS_CLOCK_DIV_M_SHIFT = 1,
29 LPSS_CLOCK_DIV_M_MASK = 0x7fff << LPSS_CLOCK_DIV_M_SHIFT,
30
31 /* These set the UART input clock speed */
32 LPSS_UART_CLK_M_VAL = 0x25a,
33 LPSS_UART_CLK_N_VAL = 0x7fff,
34 };
35
lpss_clk_update(void * regs,u32 clk_m_val,u32 clk_n_val)36 static void lpss_clk_update(void *regs, u32 clk_m_val, u32 clk_n_val)
37 {
38 u32 clk_sel;
39
40 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT |
41 clk_m_val << LPSS_CLOCK_DIV_M_SHIFT;
42 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN;
43
44 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG);
45 }
46
uart_lpss_init(void * regs)47 static void uart_lpss_init(void *regs)
48 {
49 /* Take UART out of reset */
50 lpss_reset_release(regs);
51
52 /* Set M and N divisor inputs and enable clock */
53 lpss_clk_update(regs, LPSS_UART_CLK_M_VAL, LPSS_UART_CLK_N_VAL);
54 }
55
apl_uart_init(pci_dev_t bdf,ulong base)56 void apl_uart_init(pci_dev_t bdf, ulong base)
57 {
58 /* Set UART base address */
59 pci_x86_write_config(bdf, PCI_BASE_ADDRESS_0, base, PCI_SIZE_32);
60
61 /* Enable memory access and bus master */
62 pci_x86_write_config(bdf, PCI_COMMAND, PCI_COMMAND_MEMORY |
63 PCI_COMMAND_MASTER, PCI_SIZE_32);
64
65 uart_lpss_init((void *)base);
66 }
67
68 /*
69 * This driver uses its own compatible string but almost everything else from
70 * the standard ns16550 driver. This allows us to provide an of-platdata
71 * implementation, since the platdata produced by of-platdata does not match
72 * struct apl_ns16550_plat.
73 *
74 * When running with of-platdata (generally TPL), the platdata is converted to
75 * something that ns16550 expects. When running withoutof-platdata (SPL, U-Boot
76 * proper), we use ns16550's of_to_plat routine.
77 */
78
apl_ns16550_probe(struct udevice * dev)79 static int apl_ns16550_probe(struct udevice *dev)
80 {
81 struct apl_ns16550_plat *plat = dev_get_plat(dev);
82
83 if (!CONFIG_IS_ENABLED(PCI))
84 apl_uart_init(plat->ns16550.bdf, plat->ns16550.base);
85
86 return ns16550_serial_probe(dev);
87 }
88
apl_ns16550_of_to_plat(struct udevice * dev)89 static int apl_ns16550_of_to_plat(struct udevice *dev)
90 {
91 #if CONFIG_IS_ENABLED(OF_PLATDATA)
92 struct dtd_intel_apl_ns16550 *dtplat;
93 struct apl_ns16550_plat *plat = dev_get_plat(dev);
94 struct ns16550_plat ns;
95
96 /*
97 * The device's plat uses struct apl_ns16550_plat which starts with the
98 * dtd struct, but the ns16550 driver expects it to be struct ns16550.
99 * Set up what that driver expects. Note that this means that the values
100 * cannot be read in this driver when using of-platdata.
101 *
102 * TODO(sjg@chromium.org): Consider having a separate plat pointer for
103 * of-platdata so that it is not necessary to overwrite this.
104 */
105 dtplat = &plat->dtplat;
106 ns.base = dtplat->early_regs[0];
107 ns.reg_width = 1;
108 ns.reg_shift = dtplat->reg_shift;
109 ns.reg_offset = 0;
110 ns.clock = dtplat->clock_frequency;
111 ns.fcr = UART_FCR_DEFVAL;
112 ns.bdf = pci_ofplat_get_devfn(dtplat->reg[0]);
113 memcpy(plat, &ns, sizeof(ns));
114 #else
115 int ret;
116
117 ret = ns16550_serial_of_to_plat(dev);
118 if (ret)
119 return ret;
120 #endif /* OF_PLATDATA */
121
122 return 0;
123 }
124
125 #if CONFIG_IS_ENABLED(OF_REAL)
126 static const struct udevice_id apl_ns16550_serial_ids[] = {
127 { .compatible = "intel,apl-ns16550" },
128 { },
129 };
130 #endif
131
132 U_BOOT_DRIVER(intel_apl_ns16550) = {
133 .name = "intel_apl_ns16550",
134 .id = UCLASS_SERIAL,
135 .of_match = of_match_ptr(apl_ns16550_serial_ids),
136 .plat_auto = sizeof(struct apl_ns16550_plat),
137 .priv_auto = sizeof(struct ns16550),
138 .ops = &ns16550_serial_ops,
139 .of_to_plat = apl_ns16550_of_to_plat,
140 .probe = apl_ns16550_probe,
141 };
142