1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2011 The Chromium OS Authors. 4 * (C) Copyright 2008 5 * Graeme Russ, graeme.russ@gmail.com. 6 */ 7 8 #include <cpu_func.h> 9 #include <event.h> 10 #include <fdtdec.h> 11 #include <init.h> 12 #include <usb.h> 13 #include <asm/global_data.h> 14 #include <asm/io.h> 15 #include <asm/msr.h> 16 #include <asm/mtrr.h> 17 #include <asm/cb_sysinfo.h> 18 #include <asm/arch/timestamp.h> 19 #include <dm/ofnode.h> 20 arch_cpu_init(void)21int arch_cpu_init(void) 22 { 23 int ret; 24 25 ret = IS_ENABLED(CONFIG_X86_64) ? x86_cpu_reinit_f() : 26 x86_cpu_init_f(); 27 if (ret) 28 return ret; 29 30 ret = get_coreboot_info(&lib_sysinfo); 31 if (ret != 0) { 32 printf("Failed to parse coreboot tables.\n"); 33 return ret; 34 } 35 36 timestamp_init(); 37 38 return 0; 39 } 40 board_final_init(void)41static void board_final_init(void) 42 { 43 /* 44 * Un-cache the ROM so the kernel has one 45 * more MTRR available. 46 * 47 * Coreboot should have assigned this to the 48 * top available variable MTRR. 49 */ 50 u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1; 51 u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff; 52 53 /* Make sure this MTRR is the correct Write-Protected type */ 54 if (top_type == MTRR_TYPE_WRPROT) { 55 struct mtrr_state state; 56 57 mtrr_open(&state, true); 58 wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0); 59 wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0); 60 mtrr_close(&state, true); 61 } 62 63 if (!ofnode_conf_read_bool("u-boot,no-apm-finalize")) { 64 /* 65 * Issue SMI to coreboot to lock down ME and registers 66 * when allowed via device tree 67 */ 68 printf("Finalizing coreboot\n"); 69 outb(0xcb, 0xb2); 70 } 71 } 72 last_stage_init(void)73static int last_stage_init(void) 74 { 75 timestamp_add_to_bootstage(); 76 77 if (IS_ENABLED(CONFIG_XPL_BUILD)) 78 return 0; 79 80 board_final_init(); 81 82 return 0; 83 } 84 EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init); 85