1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2014 Google Inc.
4 * Copyright (c) 2016 Google, Inc
5 * Copyright (C) 2015-2018 Intel Corporation.
6 * Copyright (C) 2018 Siemens AG
7 * Some code taken from coreboot cpulib.c
8 */
9
10 #include <cpu.h>
11 #include <dm.h>
12 #include <errno.h>
13 #include <log.h>
14 #include <acpi/acpigen.h>
15 #include <asm/cpu.h>
16 #include <asm/cpu_common.h>
17 #include <asm/global_data.h>
18 #include <asm/intel_regs.h>
19 #include <asm/lapic.h>
20 #include <asm/lpc_common.h>
21 #include <asm/msr.h>
22 #include <asm/mtrr.h>
23 #include <asm/post.h>
24 #include <asm/microcode.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
report_bist_failure(void)28 static int report_bist_failure(void)
29 {
30 if (gd->arch.bist != 0) {
31 post_code(POST_BIST_FAILURE);
32 printf("BIST failed: %08x\n", gd->arch.bist);
33 return -EFAULT;
34 }
35
36 return 0;
37 }
38
cpu_common_init(void)39 int cpu_common_init(void)
40 {
41 struct udevice *dev, *lpc;
42 int ret;
43
44 /* Halt if there was a built in self test failure */
45 ret = report_bist_failure();
46 if (ret)
47 return ret;
48
49 enable_lapic();
50
51 ret = microcode_update_intel();
52 if (ret && ret != -EEXIST) {
53 debug("%s: Microcode update failure (err=%d)\n", __func__, ret);
54 return ret;
55 }
56
57 /* Enable upper 128bytes of CMOS */
58 writel(1 << 2, RCB_REG(RC));
59
60 /* Early chipset init required before RAM init can work */
61 uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
62
63 ret = uclass_first_device_err(UCLASS_LPC, &lpc);
64 if (ret)
65 return ret;
66
67 /* Cause the SATA device to do its early init */
68 uclass_first_device(UCLASS_AHCI, &dev);
69
70 return 0;
71 }
72
cpu_set_flex_ratio_to_tdp_nominal(void)73 int cpu_set_flex_ratio_to_tdp_nominal(void)
74 {
75 msr_t flex_ratio, msr;
76 u8 nominal_ratio;
77
78 /* Check for Flex Ratio support */
79 flex_ratio = msr_read(MSR_FLEX_RATIO);
80 if (!(flex_ratio.lo & FLEX_RATIO_EN))
81 return -EINVAL;
82
83 /* Check for >0 configurable TDPs */
84 msr = msr_read(MSR_PLATFORM_INFO);
85 if (((msr.hi >> 1) & 3) == 0)
86 return -EINVAL;
87
88 /* Use nominal TDP ratio for flex ratio */
89 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
90 nominal_ratio = msr.lo & 0xff;
91
92 /* See if flex ratio is already set to nominal TDP ratio */
93 if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
94 return 0;
95
96 /* Set flex ratio to nominal TDP ratio */
97 flex_ratio.lo &= ~0xff00;
98 flex_ratio.lo |= nominal_ratio << 8;
99 flex_ratio.lo |= FLEX_RATIO_LOCK;
100 msr_write(MSR_FLEX_RATIO, flex_ratio);
101
102 /* Set flex ratio in soft reset data register bits 11:6 */
103 clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6,
104 (nominal_ratio & 0x3f) << 6);
105
106 debug("CPU: Soft reset to set up flex ratio\n");
107
108 /* Set soft reset control to use register value */
109 setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
110
111 /* Issue warm reset, will be "CPU only" due to soft reset data */
112 outb(0x0, IO_PORT_RESET);
113 outb(SYS_RST | RST_CPU, IO_PORT_RESET);
114 cpu_hlt();
115
116 /* Not reached */
117 return -EINVAL;
118 }
119
cpu_intel_get_info(struct cpu_info * info,int bclk)120 int cpu_intel_get_info(struct cpu_info *info, int bclk)
121 {
122 msr_t msr;
123
124 msr = msr_read(MSR_IA32_PERF_CTL);
125 info->cpu_freq = ((msr.lo >> 8) & 0xff) * bclk * 1000000;
126 info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
127 1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID;
128 info->address_width = cpu_phys_address_size();
129
130 return 0;
131 }
132
cpu_configure_thermal_target(struct udevice * dev)133 int cpu_configure_thermal_target(struct udevice *dev)
134 {
135 u32 tcc_offset;
136 msr_t msr;
137 int ret;
138
139 ret = dev_read_u32(dev, "tcc-offset", &tcc_offset);
140 if (!ret)
141 return -ENOENT;
142
143 /* Set TCC activaiton offset if supported */
144 msr = msr_read(MSR_PLATFORM_INFO);
145 if (msr.lo & (1 << 30)) {
146 msr = msr_read(MSR_TEMPERATURE_TARGET);
147 msr.lo &= ~(0xf << 24); /* Bits 27:24 */
148 msr.lo |= (tcc_offset & 0xf) << 24;
149 msr_write(MSR_TEMPERATURE_TARGET, msr);
150 }
151
152 return 0;
153 }
154
cpu_set_perf_control(uint clk_ratio)155 void cpu_set_perf_control(uint clk_ratio)
156 {
157 msr_t perf_ctl;
158
159 perf_ctl.lo = (clk_ratio & 0xff) << 8;
160 perf_ctl.hi = 0;
161 msr_write(MSR_IA32_PERF_CTL, perf_ctl);
162 debug("CPU: frequency set to %d MHz\n", clk_ratio * INTEL_BCLK_MHZ);
163 }
164
cpu_config_tdp_levels(void)165 bool cpu_config_tdp_levels(void)
166 {
167 msr_t platform_info;
168
169 /* Bits 34:33 indicate how many levels supported */
170 platform_info = msr_read(MSR_PLATFORM_INFO);
171
172 return ((platform_info.hi >> 1) & 3) != 0;
173 }
174
cpu_set_p_state_to_turbo_ratio(void)175 void cpu_set_p_state_to_turbo_ratio(void)
176 {
177 msr_t msr;
178
179 msr = msr_read(MSR_TURBO_RATIO_LIMIT);
180 cpu_set_perf_control(msr.lo);
181 }
182
cpu_get_burst_mode_state(void)183 enum burst_mode_t cpu_get_burst_mode_state(void)
184 {
185 enum burst_mode_t state;
186 int burst_en, burst_cap;
187 msr_t msr;
188 uint eax;
189
190 eax = cpuid_eax(0x6);
191 burst_cap = eax & 0x2;
192 msr = msr_read(MSR_IA32_MISC_ENABLE);
193 burst_en = !(msr.hi & BURST_MODE_DISABLE);
194
195 if (!burst_cap && burst_en)
196 state = BURST_MODE_UNAVAILABLE;
197 else if (burst_cap && !burst_en)
198 state = BURST_MODE_DISABLED;
199 else if (burst_cap && burst_en)
200 state = BURST_MODE_ENABLED;
201 else
202 state = BURST_MODE_UNKNOWN;
203
204 return state;
205 }
206
cpu_set_burst_mode(bool burst_mode)207 void cpu_set_burst_mode(bool burst_mode)
208 {
209 msr_t msr;
210
211 msr = msr_read(MSR_IA32_MISC_ENABLE);
212 if (burst_mode)
213 msr.hi &= ~BURST_MODE_DISABLE;
214 else
215 msr.hi |= BURST_MODE_DISABLE;
216 msr_write(MSR_IA32_MISC_ENABLE, msr);
217 }
218
cpu_set_eist(bool eist_status)219 void cpu_set_eist(bool eist_status)
220 {
221 msr_t msr;
222
223 msr = msr_read(MSR_IA32_MISC_ENABLE);
224 if (eist_status)
225 msr.lo |= MISC_ENABLE_ENHANCED_SPEEDSTEP;
226 else
227 msr.lo &= ~MISC_ENABLE_ENHANCED_SPEEDSTEP;
228 msr_write(MSR_IA32_MISC_ENABLE, msr);
229 }
230
cpu_get_coord_type(void)231 int cpu_get_coord_type(void)
232 {
233 return HW_ALL;
234 }
235
cpu_get_min_ratio(void)236 int cpu_get_min_ratio(void)
237 {
238 msr_t msr;
239
240 /* Get bus ratio limits and calculate clock speeds */
241 msr = msr_read(MSR_PLATFORM_INFO);
242
243 return (msr.hi >> 8) & 0xff; /* Max Efficiency Ratio */
244 }
245
cpu_get_max_ratio(void)246 int cpu_get_max_ratio(void)
247 {
248 u32 ratio_max;
249 msr_t msr;
250
251 if (cpu_config_tdp_levels()) {
252 /* Set max ratio to nominal TDP ratio */
253 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
254 ratio_max = msr.lo & 0xff;
255 } else {
256 msr = msr_read(MSR_PLATFORM_INFO);
257 /* Max Non-Turbo Ratio */
258 ratio_max = (msr.lo >> 8) & 0xff;
259 }
260
261 return ratio_max;
262 }
263
cpu_get_bus_clock_khz(void)264 int cpu_get_bus_clock_khz(void)
265 {
266 /*
267 * CPU bus clock is set by default here to 100MHz. This function returns
268 * the bus clock in KHz.
269 */
270 return INTEL_BCLK_MHZ * 1000;
271 }
272
cpu_get_power_max(void)273 int cpu_get_power_max(void)
274 {
275 int power_unit;
276 msr_t msr;
277
278 msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
279 power_unit = 2 << ((msr.lo & 0xf) - 1);
280 msr = msr_read(MSR_PKG_POWER_SKU);
281
282 return (msr.lo & 0x7fff) * 1000 / power_unit;
283 }
284
cpu_get_max_turbo_ratio(void)285 int cpu_get_max_turbo_ratio(void)
286 {
287 msr_t msr;
288
289 msr = msr_read(MSR_TURBO_RATIO_LIMIT);
290
291 return msr.lo & 0xff;
292 }
293
cpu_get_cores_per_package(void)294 int cpu_get_cores_per_package(void)
295 {
296 struct cpuid_result result;
297 int cores = 1;
298
299 if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
300 return 1;
301
302 result = cpuid_ext(0xb, 1);
303 cores = result.ebx & 0xff;
304
305 return cores;
306 }
307
cpu_mca_configure(void)308 void cpu_mca_configure(void)
309 {
310 msr_t msr;
311 int i;
312 int num_banks;
313
314 msr = msr_read(MSR_IA32_MCG_CAP);
315 num_banks = msr.lo & 0xff;
316 msr.lo = 0;
317 msr.hi = 0;
318 for (i = 0; i < num_banks; i++) {
319 /* Clear the machine check status */
320 msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr);
321 /* Initialise machine checks */
322 msr_write(MSR_IA32_MC0_CTL + i * 4,
323 (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff});
324 }
325 }
326