1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 4 * Copyright (C) 2016 Stefan Roese <sr@denx.de> 5 */ 6 7/dts-v1/; 8 9#include <asm/arch-baytrail/fsp/fsp_configs.h> 10#include <dt-bindings/gpio/x86-gpio.h> 11#include <dt-bindings/interrupt-router/intel-irq.h> 12 13/include/ "skeleton.dtsi" 14/include/ "serial.dtsi" 15/include/ "reset.dtsi" 16/include/ "rtc.dtsi" 17 18#include "tsc_timer.dtsi" 19#include "smbios.dtsi" 20 21/ { 22 model = "congatec-QEVAL20-QA3-E3845"; 23 compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail"; 24 25 aliases { 26 serial0 = &serial; 27 spi0 = &spi; 28 }; 29 30 config { 31 silent_console = <0>; 32 }; 33 34 pch_pinctrl { 35 compatible = "intel,x86-pinctrl"; 36 reg = <0 0>; 37 38 /* 39 * As of today, the latest version FSP (gold4) for BayTrail 40 * misses the PAD configuration of the SD controller's Card 41 * Detect signal. The default PAD value for the CD pin sets 42 * the pin to work in GPIO mode, which causes card detect 43 * status cannot be reflected by the Present State register 44 * in the SD controller (bit 16 & bit 18 are always zero). 45 * 46 * Configure this pin to function 1 (SD controller). 47 */ 48 sdmmc3_cd@0 { 49 pad-offset = <0x3a0>; 50 mode-func = <1>; 51 }; 52 53 /* Add SMBus PAD configuration */ 54 smbus_clk@0 { 55 pad-offset = <0x580>; 56 mode-func = <1>; 57 }; 58 59 smbus_data@0 { 60 pad-offset = <0x5a0>; 61 mode-func = <1>; 62 }; 63 }; 64 65 chosen { 66 stdout-path = "/serial"; 67 }; 68 69 cpus { 70 #address-cells = <1>; 71 #size-cells = <0>; 72 73 cpu@0 { 74 device_type = "cpu"; 75 compatible = "intel,baytrail-cpu"; 76 reg = <0>; 77 intel,apic-id = <0>; 78 }; 79 80 cpu@1 { 81 device_type = "cpu"; 82 compatible = "intel,baytrail-cpu"; 83 reg = <1>; 84 intel,apic-id = <2>; 85 }; 86 87 cpu@2 { 88 device_type = "cpu"; 89 compatible = "intel,baytrail-cpu"; 90 reg = <2>; 91 intel,apic-id = <4>; 92 }; 93 94 cpu@3 { 95 device_type = "cpu"; 96 compatible = "intel,baytrail-cpu"; 97 reg = <3>; 98 intel,apic-id = <6>; 99 }; 100 }; 101 102 pci { 103 compatible = "intel,pci-baytrail", "pci-x86"; 104 #address-cells = <3>; 105 #size-cells = <2>; 106 bootph-all; 107 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 108 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 109 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 110 111 pch@1f,0 { 112 reg = <0x0000f800 0 0 0 0>; 113 compatible = "pci8086,0f1c", "intel,pch9"; 114 #address-cells = <1>; 115 #size-cells = <1>; 116 117 irq-router { 118 compatible = "intel,irq-router"; 119 intel,pirq-config = "ibase"; 120 intel,ibase-offset = <0x50>; 121 intel,actl-addr = <0>; 122 intel,pirq-link = <8 8>; 123 intel,pirq-mask = <0xdee0>; 124 intel,pirq-routing = < 125 /* BayTrail PCI devices */ 126 PCI_BDF(0, 2, 0) INTA PIRQA 127 PCI_BDF(0, 3, 0) INTA PIRQA 128 PCI_BDF(0, 16, 0) INTA PIRQA 129 PCI_BDF(0, 17, 0) INTA PIRQA 130 PCI_BDF(0, 18, 0) INTA PIRQA 131 PCI_BDF(0, 19, 0) INTA PIRQA 132 PCI_BDF(0, 20, 0) INTA PIRQA 133 PCI_BDF(0, 21, 0) INTA PIRQA 134 PCI_BDF(0, 22, 0) INTA PIRQA 135 PCI_BDF(0, 23, 0) INTA PIRQA 136 PCI_BDF(0, 24, 0) INTA PIRQA 137 PCI_BDF(0, 24, 1) INTC PIRQC 138 PCI_BDF(0, 24, 2) INTD PIRQD 139 PCI_BDF(0, 24, 3) INTB PIRQB 140 PCI_BDF(0, 24, 4) INTA PIRQA 141 PCI_BDF(0, 24, 5) INTC PIRQC 142 PCI_BDF(0, 24, 6) INTD PIRQD 143 PCI_BDF(0, 24, 7) INTB PIRQB 144 PCI_BDF(0, 26, 0) INTA PIRQA 145 PCI_BDF(0, 27, 0) INTA PIRQA 146 PCI_BDF(0, 28, 0) INTA PIRQA 147 PCI_BDF(0, 28, 1) INTB PIRQB 148 PCI_BDF(0, 28, 2) INTC PIRQC 149 PCI_BDF(0, 28, 3) INTD PIRQD 150 PCI_BDF(0, 29, 0) INTA PIRQA 151 PCI_BDF(0, 30, 0) INTA PIRQA 152 PCI_BDF(0, 30, 1) INTD PIRQD 153 PCI_BDF(0, 30, 2) INTB PIRQB 154 PCI_BDF(0, 30, 3) INTC PIRQC 155 PCI_BDF(0, 30, 4) INTD PIRQD 156 PCI_BDF(0, 30, 5) INTB PIRQB 157 PCI_BDF(0, 31, 3) INTB PIRQB 158 159 /* 160 * PCIe root ports downstream 161 * interrupts 162 */ 163 PCI_BDF(1, 0, 0) INTA PIRQA 164 PCI_BDF(1, 0, 0) INTB PIRQB 165 PCI_BDF(1, 0, 0) INTC PIRQC 166 PCI_BDF(1, 0, 0) INTD PIRQD 167 PCI_BDF(2, 0, 0) INTA PIRQB 168 PCI_BDF(2, 0, 0) INTB PIRQC 169 PCI_BDF(2, 0, 0) INTC PIRQD 170 PCI_BDF(2, 0, 0) INTD PIRQA 171 PCI_BDF(3, 0, 0) INTA PIRQC 172 PCI_BDF(3, 0, 0) INTB PIRQD 173 PCI_BDF(3, 0, 0) INTC PIRQA 174 PCI_BDF(3, 0, 0) INTD PIRQB 175 PCI_BDF(4, 0, 0) INTA PIRQD 176 PCI_BDF(4, 0, 0) INTB PIRQA 177 PCI_BDF(4, 0, 0) INTC PIRQB 178 PCI_BDF(4, 0, 0) INTD PIRQC 179 >; 180 }; 181 182 spi: spi { 183 #address-cells = <1>; 184 #size-cells = <0>; 185 compatible = "intel,ich9-spi"; 186 spi-flash@0 { 187 #address-cells = <1>; 188 #size-cells = <1>; 189 reg = <0>; 190 m25p,fast-read; 191 compatible = "stmicro,n25q064a", 192 "jedec,spi-nor"; 193 memory-map = <0xff800000 0x00800000>; 194 rw-mrc-cache { 195 label = "rw-mrc-cache"; 196 reg = <0x005f0000 0x00010000>; 197 }; 198 }; 199 }; 200 201 gpioa { 202 compatible = "intel,ich6-gpio"; 203 bootph-all; 204 reg = <0 0x20>; 205 bank-name = "A"; 206 use-lvl-write-cache; 207 }; 208 209 gpiob { 210 compatible = "intel,ich6-gpio"; 211 bootph-all; 212 reg = <0x20 0x20>; 213 bank-name = "B"; 214 use-lvl-write-cache; 215 }; 216 217 gpioc { 218 compatible = "intel,ich6-gpio"; 219 bootph-all; 220 reg = <0x40 0x20>; 221 bank-name = "C"; 222 use-lvl-write-cache; 223 }; 224 225 gpiod { 226 compatible = "intel,ich6-gpio"; 227 bootph-all; 228 reg = <0x60 0x20>; 229 bank-name = "D"; 230 use-lvl-write-cache; 231 }; 232 233 gpioe { 234 compatible = "intel,ich6-gpio"; 235 bootph-all; 236 reg = <0x80 0x20>; 237 bank-name = "E"; 238 use-lvl-write-cache; 239 }; 240 241 gpiof { 242 compatible = "intel,ich6-gpio"; 243 bootph-all; 244 reg = <0xA0 0x20>; 245 bank-name = "F"; 246 use-lvl-write-cache; 247 }; 248 }; 249 }; 250 251 fsp { 252 compatible = "intel,baytrail-fsp"; 253 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>; 254 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>; 255 fsp,mrc-init-spd-addr1 = <0xa0>; 256 fsp,mrc-init-spd-addr2 = <0xa2>; 257 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>; 258 fsp,enable-sdio; 259 fsp,enable-sdcard; 260 fsp,enable-hsuart1; 261 fsp,enable-spi; 262 fsp,enable-sata; 263 fsp,sata-mode = <SATA_MODE_AHCI>; 264#ifdef CONFIG_USB_XHCI_HCD 265 fsp,enable-xhci; 266#endif 267 fsp,lpe-mode = <LPE_MODE_PCI>; 268 fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>; 269 fsp,enable-dma0; 270 fsp,enable-dma1; 271 fsp,enable-pwm0; 272 fsp,enable-pwm1; 273 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>; 274 fsp,aperture-size = <APERTURE_SIZE_256MB>; 275 fsp,gtt-size = <GTT_SIZE_2MB>; 276 fsp,scc-mode = <SCC_MODE_PCI>; 277 fsp,os-selection = <OS_SELECTION_LINUX>; 278 fsp,emmc45-ddr50-enabled; 279 fsp,emmc45-retune-timer-value = <8>; 280 fsp,enable-igd; 281 fsp,enable-memory-down; 282 fsp,memory-down-params { 283 compatible = "intel,baytrail-fsp-mdp"; 284 fsp,dram-speed = <DRAM_SPEED_1333MTS>; 285 fsp,dram-type = <DRAM_TYPE_DDR3L>; 286 fsp,dimm-0-enable; 287 fsp,dimm-1-enable; 288 fsp,dimm-width = <DIMM_WIDTH_X16>; 289 fsp,dimm-density = <DIMM_DENSITY_4GBIT>; 290 fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>; 291 fsp,dimm-sides = <DIMM_SIDES_1RANKS>; 292 293 /* These following values might need a re-visit */ 294 fsp,dimm-tcl = <8>; 295 fsp,dimm-trpt-rcd = <8>; 296 fsp,dimm-twr = <8>; 297 fsp,dimm-twtr = <4>; 298 fsp,dimm-trrd = <6>; 299 fsp,dimm-trtp = <4>; 300 fsp,dimm-tfaw = <22>; 301 }; 302 }; 303 304 microcode { 305 update@0 { 306#include "microcode/m0130673325.dtsi" 307 }; 308 update@1 { 309#include "microcode/m0130679907.dtsi" 310 }; 311 }; 312}; 313