1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 4 */ 5 6/dts-v1/; 7 8#include <asm/arch-baytrail/fsp/fsp_configs.h> 9#include <dt-bindings/gpio/x86-gpio.h> 10#include <dt-bindings/interrupt-router/intel-irq.h> 11 12/include/ "skeleton.dtsi" 13/include/ "serial.dtsi" 14/include/ "reset.dtsi" 15/include/ "rtc.dtsi" 16 17#include "tsc_timer.dtsi" 18#include "smbios.dtsi" 19 20/ { 21 model = "Intel Minnowboard Max"; 22 compatible = "intel,minnowmax", "intel,baytrail"; 23 24 aliases { 25 serial0 = &serial; 26 spi0 = &spi; 27 }; 28 29 config { 30 silent_console = <0>; 31 }; 32 33 pch_pinctrl { 34 compatible = "intel,x86-pinctrl"; 35 reg = <0 0>; 36 37 /* GPIO E0 */ 38 soc_gpio_s5_0@0 { 39 gpio-offset = <0x80 0>; 40 mode-gpio; 41 output-value = <0>; 42 direction = <PIN_OUTPUT>; 43 }; 44 45 /* GPIO E1 */ 46 soc_gpio_s5_1@0 { 47 gpio-offset = <0x80 1>; 48 mode-gpio; 49 output-value = <0>; 50 direction = <PIN_OUTPUT>; 51 }; 52 53 /* GPIO E2 */ 54 soc_gpio_s5_2@0 { 55 gpio-offset = <0x80 2>; 56 mode-gpio; 57 output-value = <0>; 58 direction = <PIN_OUTPUT>; 59 }; 60 61 pin_usb_host_en0@0 { 62 gpio-offset = <0x80 8>; 63 mode-gpio; 64 output-value = <1>; 65 direction = <PIN_OUTPUT>; 66 }; 67 68 pin_usb_host_en1@0 { 69 gpio-offset = <0x80 9>; 70 mode-gpio; 71 output-value = <1>; 72 direction = <PIN_OUTPUT>; 73 }; 74 75 /* 76 * As of today, the latest version FSP (gold4) for BayTrail 77 * misses the PAD configuration of the SD controller's Card 78 * Detect signal. The default PAD value for the CD pin sets 79 * the pin to work in GPIO mode, which causes card detect 80 * status cannot be reflected by the Present State register 81 * in the SD controller (bit 16 & bit 18 are always zero). 82 * 83 * Configure this pin to function 1 (SD controller). 84 */ 85 sdmmc3_cd@0 { 86 pad-offset = <0x3a0>; 87 mode-func = <1>; 88 }; 89 }; 90 91 chosen { 92 stdout-path = "/serial"; 93 }; 94 95 cpus { 96 #address-cells = <1>; 97 #size-cells = <0>; 98 99 cpu@0 { 100 device_type = "cpu"; 101 compatible = "intel,baytrail-cpu"; 102 reg = <0>; 103 intel,apic-id = <0>; 104 }; 105 106 cpu@1 { 107 device_type = "cpu"; 108 compatible = "intel,baytrail-cpu"; 109 reg = <1>; 110 intel,apic-id = <4>; 111 }; 112 113 }; 114 115 pci { 116 compatible = "intel,pci-baytrail", "pci-x86"; 117 #address-cells = <3>; 118 #size-cells = <2>; 119 bootph-all; 120 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 121 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 122 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 123 124 pch@1f,0 { 125 reg = <0x0000f800 0 0 0 0>; 126 compatible = "pci8086,0f1c", "intel,pch9"; 127 #address-cells = <1>; 128 #size-cells = <1>; 129 130 irq-router { 131 compatible = "intel,irq-router"; 132 intel,pirq-config = "ibase"; 133 intel,ibase-offset = <0x50>; 134 intel,actl-addr = <0>; 135 intel,pirq-link = <8 8>; 136 intel,pirq-mask = <0xdee0>; 137 intel,pirq-routing = < 138 /* BayTrail PCI devices */ 139 PCI_BDF(0, 2, 0) INTA PIRQA 140 PCI_BDF(0, 3, 0) INTA PIRQA 141 PCI_BDF(0, 16, 0) INTA PIRQA 142 PCI_BDF(0, 17, 0) INTA PIRQA 143 PCI_BDF(0, 18, 0) INTA PIRQA 144 PCI_BDF(0, 19, 0) INTA PIRQA 145 PCI_BDF(0, 20, 0) INTA PIRQA 146 PCI_BDF(0, 21, 0) INTA PIRQA 147 PCI_BDF(0, 22, 0) INTA PIRQA 148 PCI_BDF(0, 23, 0) INTA PIRQA 149 PCI_BDF(0, 24, 0) INTA PIRQA 150 PCI_BDF(0, 24, 1) INTC PIRQC 151 PCI_BDF(0, 24, 2) INTD PIRQD 152 PCI_BDF(0, 24, 3) INTB PIRQB 153 PCI_BDF(0, 24, 4) INTA PIRQA 154 PCI_BDF(0, 24, 5) INTC PIRQC 155 PCI_BDF(0, 24, 6) INTD PIRQD 156 PCI_BDF(0, 24, 7) INTB PIRQB 157 PCI_BDF(0, 26, 0) INTA PIRQA 158 PCI_BDF(0, 27, 0) INTA PIRQA 159 PCI_BDF(0, 28, 0) INTA PIRQA 160 PCI_BDF(0, 28, 1) INTB PIRQB 161 PCI_BDF(0, 28, 2) INTC PIRQC 162 PCI_BDF(0, 28, 3) INTD PIRQD 163 PCI_BDF(0, 29, 0) INTA PIRQA 164 PCI_BDF(0, 30, 0) INTA PIRQA 165 PCI_BDF(0, 30, 1) INTD PIRQD 166 PCI_BDF(0, 30, 2) INTB PIRQB 167 PCI_BDF(0, 30, 3) INTC PIRQC 168 PCI_BDF(0, 30, 4) INTD PIRQD 169 PCI_BDF(0, 30, 5) INTB PIRQB 170 PCI_BDF(0, 31, 3) INTB PIRQB 171 172 /* 173 * PCIe root ports downstream 174 * interrupts 175 */ 176 PCI_BDF(1, 0, 0) INTA PIRQA 177 PCI_BDF(1, 0, 0) INTB PIRQB 178 PCI_BDF(1, 0, 0) INTC PIRQC 179 PCI_BDF(1, 0, 0) INTD PIRQD 180 PCI_BDF(2, 0, 0) INTA PIRQB 181 PCI_BDF(2, 0, 0) INTB PIRQC 182 PCI_BDF(2, 0, 0) INTC PIRQD 183 PCI_BDF(2, 0, 0) INTD PIRQA 184 PCI_BDF(3, 0, 0) INTA PIRQC 185 PCI_BDF(3, 0, 0) INTB PIRQD 186 PCI_BDF(3, 0, 0) INTC PIRQA 187 PCI_BDF(3, 0, 0) INTD PIRQB 188 PCI_BDF(4, 0, 0) INTA PIRQD 189 PCI_BDF(4, 0, 0) INTB PIRQA 190 PCI_BDF(4, 0, 0) INTC PIRQB 191 PCI_BDF(4, 0, 0) INTD PIRQC 192 >; 193 }; 194 195 spi: spi { 196 #address-cells = <1>; 197 #size-cells = <0>; 198 compatible = "intel,ich9-spi"; 199 spi-flash@0 { 200 #address-cells = <1>; 201 #size-cells = <1>; 202 reg = <0>; 203 m25p,fast-read; 204 compatible = "stmicro,n25q064a", 205 "jedec,spi-nor"; 206 memory-map = <0xff800000 0x00800000>; 207 rw-mrc-cache { 208 label = "rw-mrc-cache"; 209 reg = <0x005f0000 0x00010000>; 210 }; 211 }; 212 }; 213 214 gpioa { 215 compatible = "intel,ich6-gpio"; 216 bootph-all; 217 reg = <0 0x20>; 218 bank-name = "A"; 219 use-lvl-write-cache; 220 }; 221 222 gpiob { 223 compatible = "intel,ich6-gpio"; 224 bootph-all; 225 reg = <0x20 0x20>; 226 bank-name = "B"; 227 use-lvl-write-cache; 228 }; 229 230 gpioc { 231 compatible = "intel,ich6-gpio"; 232 bootph-all; 233 reg = <0x40 0x20>; 234 bank-name = "C"; 235 use-lvl-write-cache; 236 }; 237 238 gpiod { 239 compatible = "intel,ich6-gpio"; 240 bootph-all; 241 reg = <0x60 0x20>; 242 bank-name = "D"; 243 use-lvl-write-cache; 244 }; 245 246 gpioe { 247 compatible = "intel,ich6-gpio"; 248 bootph-all; 249 reg = <0x80 0x20>; 250 bank-name = "E"; 251 use-lvl-write-cache; 252 }; 253 254 gpiof { 255 compatible = "intel,ich6-gpio"; 256 bootph-all; 257 reg = <0xA0 0x20>; 258 bank-name = "F"; 259 use-lvl-write-cache; 260 }; 261 }; 262 }; 263 264 fsp { 265 compatible = "intel,baytrail-fsp"; 266 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>; 267 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>; 268 fsp,mrc-init-spd-addr1 = <0xa0>; 269 fsp,mrc-init-spd-addr2 = <0xa2>; 270 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>; 271 fsp,enable-sdio; 272 fsp,enable-sdcard; 273 fsp,enable-hsuart1; 274 fsp,enable-spi; 275 fsp,enable-sata; 276 fsp,sata-mode = <SATA_MODE_AHCI>; 277#ifdef CONFIG_USB_XHCI_HCD 278 fsp,enable-xhci; 279#endif 280 fsp,lpe-mode = <LPE_MODE_PCI>; 281 fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>; 282 fsp,enable-dma0; 283 fsp,enable-dma1; 284 fsp,enable-i2c0; 285 fsp,enable-i2c1; 286 fsp,enable-i2c2; 287 fsp,enable-i2c3; 288 fsp,enable-i2c4; 289 fsp,enable-i2c5; 290 fsp,enable-i2c6; 291 fsp,enable-pwm0; 292 fsp,enable-pwm1; 293 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>; 294 fsp,aperture-size = <APERTURE_SIZE_256MB>; 295 fsp,gtt-size = <GTT_SIZE_2MB>; 296 fsp,scc-mode = <SCC_MODE_PCI>; 297 fsp,os-selection = <OS_SELECTION_LINUX>; 298 fsp,emmc45-ddr50-enabled; 299 fsp,emmc45-retune-timer-value = <8>; 300 fsp,enable-igd; 301 fsp,enable-memory-down; 302 fsp,memory-down-params { 303 compatible = "intel,baytrail-fsp-mdp"; 304 fsp,dram-speed = <DRAM_SPEED_1066MTS>; 305 fsp,dram-type = <DRAM_TYPE_DDR3L>; 306 fsp,dimm-0-enable; 307 fsp,dimm-width = <DIMM_WIDTH_X16>; 308 fsp,dimm-density = <DIMM_DENSITY_4GBIT>; 309 fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>; 310 fsp,dimm-sides = <DIMM_SIDES_1RANKS>; 311 fsp,dimm-tcl = <0xb>; 312 fsp,dimm-trpt-rcd = <0xb>; 313 fsp,dimm-twr = <0xc>; 314 fsp,dimm-twtr = <6>; 315 fsp,dimm-trrd = <6>; 316 fsp,dimm-trtp = <6>; 317 fsp,dimm-tfaw = <0x14>; 318 }; 319 }; 320 321 microcode { 322 update@0 { 323#include "microcode/m0130673325.dtsi" 324 }; 325 update@1 { 326#include "microcode/m0130679907.dtsi" 327 }; 328 }; 329 330}; 331