1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * This file is part of the libpayload project. 4 * 5 * Copyright (C) 2008 Advanced Micro Devices, Inc. 6 */ 7 8 #ifndef _COREBOOT_SYSINFO_H 9 #define _COREBOOT_SYSINFO_H 10 11 #include <asm/coreboot_tables.h> 12 #include <linux/types.h> 13 14 /* Maximum number of memory range definitions */ 15 #define SYSINFO_MAX_MEM_RANGES 32 16 /* Allow a maximum of 8 GPIOs */ 17 #define SYSINFO_MAX_GPIOS 8 18 /* Up to 10 MAC addresses */ 19 #define SYSINFO_MAX_MACS 10 20 /* Track the first 32 unimplemented tags */ 21 #define SYSINFO_MAX_UNIMPL 32 22 23 /** 24 * struct sysinfo_t - Information passed to U-Boot from coreboot 25 * 26 * Coreboot passes on a lot of information using a list of individual data 27 * structures identified by a numeric tag. These are parsed in U-Boot to produce 28 * this struct. Some of the pointers here point back to the tagged data 29 * structure, since it is assumed to remain around while U-Boot is running. 30 * 31 * The 'cbsysinfo' command can display this information. 32 * 33 * @cpu_khz: CPU frequence in KHz (e.g. 1100000) 34 * @serial: Pointer to the serial information, NULL if none 35 * @ser_ioport: Not actually provided by a tag and not used on modern hardware, 36 * which typicaally uses a memory-mapped port 37 * @ser_base: Not used at all, but present to match up with the coreboot data 38 * structure 39 * @n_memranges: Number of memory ranges 40 * @memrange: List of memory ranges: 41 * @base: Base address of range 42 * @size: Size of range in bytes 43 * @type: Type of range (CB_MEM_RAM, etc.) 44 * @option_table: Provides a pointer to the CMOS RAM options table, which 45 * indicates which options are available. The header is followed by a list 46 * of struct cb_cmos_entries records, so that an option can be found from 47 * its name. This is not used in U-Boot. NULL if not present 48 * @cmos_range_start: Start bit of the CMOS checksum range (in fact this must 49 * be a multiple of 8) 50 * @cmos_range_end: End bit of the CMOS checksum range (multiple of 8). This is 51 * the inclusive end. 52 * @cmos_checksum_location: Location of checksum, multiplied by 8. This is the 53 * byte offset into the CMOS RAM of the first checksum byte. The second one 54 * follows immediately. The checksum is a simple 16-bit sum of all the 55 * bytes from offset cmos_range_start / 8 to cmos_range_end / 8, inclusive, 56 * in big-endian format (so sum >> 8 is stored in the first byte). 57 * @vbnv_start: Start offset of CMOS RAM used for Chromium OS verified boot 58 * (typically 0x34) 59 * @vbnv_size: Number of bytes used by Chromium OS verified boot (typically 60 * 0x10) 61 * @extra_version: Extra version information, typically "" 62 * @build: Build date, e.g. "Wed Nov 18 02:51:58 UTC 2020" 63 * @compile_time: Compilation time, e.g. "02:51:58" 64 * @compile_by: Who compiled coreboot (never set?) 65 * @compile_host: Name of the machine that compiled coreboot (never set?) 66 * @compile_domain: Domain name of the machine that compiled coreboot (never 67 * set?) 68 * @compiler: Name of the compiler used to build coreboot (never set?) 69 * @linker: Name of the linker used to build coreboot (never set?) 70 * @assembler: Name of the assembler used to build coreboot (never set?) 71 * @cb_version: Coreboot version string, e.g. v1.9308_26_0.0.22-2599-g232f22c75d 72 * @framebuffer: Address of framebuffer tag, or NULL if none. See 73 * struct cb_framebuffer for the definition 74 * @num_gpios: Number of verified-boot GPIOs 75 * @gpios: List of GPIOs: 76 * @port: GPIO number, or 0xffffffff if not a GPIO 77 * @polarity: CB_GPIO_ACTIVE_LOW or CB_GPIO_ACTIVE_HIGH 78 * @value: Value of GPIO (0 or 1) 79 * @name: Name of GPIO 80 * 81 * A typical list is: 82 * id: port polarity val name 83 * 0: - active-high 1 write protect 84 * 1: - active-high 0 recovery 85 * 2: - active-high 1 lid 86 * 3: - active-high 0 power 87 * 4: - active-high 0 oprom 88 * 5: 29 active-high 0 EC in RW 89 * 90 * @num_macs: Number of MAC addresses 91 * @macs: List of MAC addresses 92 * @serialno: Serial number, or NULL (never set?) 93 * @mbtable: Address of the multiboot table, or NULL. This is a 94 * struct multiboot_header, not used in U-Boot 95 * @header: Address of header, if there is a CB_TAG_FORWARD, else NULL 96 * @mainboard: Pointer to mainboard info or NULL. Typically the vendor is 97 * "Google" and the part number is "" 98 * @vboot_handoff: Pointer to Chromium OS verified boot hand-off information. 99 * This is struct vboot_handoff, providing access to internal information 100 * generated by coreboot when this is being used 101 * @vboot_handoff_size: Size of hand-off information (typically 0xc0c) 102 * @vdat_addr: Pointer to Chromium OS verified boot data, which uses 103 * struct chromeos_acpi. It sits in the Intel Global NVS struct, after the 104 * first 0x100 bytes 105 * @vdat_size: Size of this data, typically 0xf00 106 * @smbios_start: Address of SMBIOS tables 107 * @smbios_size: Size of SMBIOS tables (e.g. 0x800) 108 * @x86_rom_var_mtrr_index: MTRR number used for ROM caching. Not used in U-Boot 109 * @tstamp_table: Pointer to timestamp_table, struct timestamp_table 110 * @cbmem_cons: Pointer to the console dump, struct cbmem_console. This provides 111 * access to the console output generated by coreboot, typically about 64KB 112 * and mostly PCI enumeration info 113 * @mrc_cache: Pointer to memory-reference-code cache, typically NULL 114 * acpi_gnvs: @Pointer to Intel Global NVS struct, see struct acpi_global_nvs 115 * @board_id: Board ID indicating the board variant, typically 0xffffffff 116 * @ram_code: RAM code indicating the SDRAM type, typically 0xffffffff 117 * @wifi_calibration: WiFi calibration info, NULL if none 118 * @ramoops_buffer: Address of kernel Ramoops buffer 119 * @ramoops_buffer_size: Sizeof of Ramoops buffer, typically 1MB 120 * @spi_flash: Information about SPI flash: 121 * @size: Size in bytes, e.g. 16MB 122 * @sector_size; Sector size of flash device, e.g. 4KB 123 * @erase_cmd: Command used to erase flash, or 0 if not used 124 * @fmap_offset: SPI-flash offset of the flash map (FMAP) table. This has a 125 * __FMAP__ header. It provides information about the different top-level 126 * sections in the SPI flash, e.g. 0x204000 127 * @cbfs_offset: SPI-flash offset of the Coreboot Filesystem (CBFS) used for 128 * read-only data, e.g. 0x205000. This is typically called 'COREBOOT' in 129 * the flash map. It holds various coreboot binaries as well as 130 * video-configuration files and graphics data for the Chromium OS 131 * verified boot user interface. 132 * @cbfs_size: Size of CBFS, e.g. 0x17b000 133 * @boot_media_size; Size of boot media (i.e. SPI flash), e.g. 16MB 134 * @mtc_start; Start of MTC region (Nvidia private data), 0 if not used. See 135 * https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/nvidia/tegra210/mtc.c 136 * @mtc_size: Size of MTC region 137 * @chromeos_vpd: Chromium OS Vital Product Data region, typically NULL, meaning 138 * not used 139 * @rsdp: Pointer to ACPI RSDP table 140 * @unimpl_count: Number of entries in unimpl_map[] 141 * @unimpl: List of unimplemented IDs (bottom 8 bits only) 142 * @table_size: Number of bytes taken up by the sysinfo table 143 * @rec_count: Number of records in the sysinfo table 144 */ 145 struct sysinfo_t { 146 unsigned int cpu_khz; 147 struct cb_serial *serial; 148 unsigned short ser_ioport; 149 unsigned long ser_base; // for mmapped serial 150 151 int n_memranges; 152 153 struct memrange { 154 unsigned long long base; 155 unsigned long long size; 156 unsigned int type; 157 } memrange[SYSINFO_MAX_MEM_RANGES]; 158 159 struct cb_cmos_option_table *option_table; 160 u32 cmos_range_start; 161 u32 cmos_range_end; 162 u32 cmos_checksum_location; 163 u32 vbnv_start; 164 u32 vbnv_size; 165 166 char *version; 167 char *extra_version; 168 char *build; 169 char *compile_time; 170 char *compile_by; 171 char *compile_host; 172 char *compile_domain; 173 char *compiler; 174 char *linker; 175 char *assembler; 176 177 char *cb_version; 178 179 struct cb_framebuffer *framebuffer; 180 181 int num_gpios; 182 struct cb_gpio gpios[SYSINFO_MAX_GPIOS]; 183 int num_macs; 184 struct mac_address macs[SYSINFO_MAX_MACS]; 185 char *serialno; 186 187 unsigned long *mbtable; /** Pointer to the multiboot table */ 188 189 struct cb_header *header; 190 struct cb_mainboard *mainboard; 191 192 void *vboot_handoff; 193 u32 vboot_handoff_size; 194 void *vdat_addr; 195 u32 vdat_size; 196 u64 smbios_start; 197 u32 smbios_size; 198 199 int x86_rom_var_mtrr_index; 200 201 void *tstamp_table; 202 void *cbmem_cons; 203 void *mrc_cache; 204 void *acpi_gnvs; 205 u32 board_id; 206 u32 ram_code; 207 void *wifi_calibration; 208 u64 ramoops_buffer; 209 u32 ramoops_buffer_size; 210 struct { 211 u32 size; 212 u32 sector_size; 213 u32 erase_cmd; 214 } spi_flash; 215 u64 fmap_offset; 216 u64 cbfs_offset; 217 u64 cbfs_size; 218 u64 boot_media_size; 219 u64 mtc_start; 220 u32 mtc_size; 221 void *chromeos_vpd; 222 void *rsdp; 223 u32 unimpl_count; 224 u8 unimpl[SYSINFO_MAX_UNIMPL]; 225 uint table_size; 226 uint rec_count; 227 }; 228 229 extern struct sysinfo_t lib_sysinfo; 230 231 /** 232 * get_coreboot_info() - parse the coreboot sysinfo table 233 * 234 * Parses the coreboot table if found, setting the GD_FLG_SKIP_LL_INIT flag if 235 * so. 236 * 237 * @info: Place to put the parsed information 238 * Return: 0 if OK, -ENOENT if no table found 239 */ 240 int get_coreboot_info(struct sysinfo_t *info); 241 242 /** 243 * cb_get_sysinfo() - get a pointer to the parsed coreboot sysinfo 244 * 245 * Return: pointer to sysinfo, or NULL if not available 246 */ 247 const struct sysinfo_t *cb_get_sysinfo(void); 248 249 #endif 250