1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2002
4  * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
5  */
6 
7 #ifndef __ASM_PROCESSOR_H_
8 #define __ASM_PROCESSOR_H_ 1
9 
10 #define X86_GDT_ENTRY_SIZE		8
11 
12 #define X86_GDT_ENTRY_NULL		0
13 #define X86_GDT_ENTRY_UNUSED		1
14 #define X86_GDT_ENTRY_32BIT_CS		2
15 #define X86_GDT_ENTRY_32BIT_DS		3
16 #define X86_GDT_ENTRY_32BIT_FS		4
17 #define X86_GDT_ENTRY_16BIT_CS		5
18 #define X86_GDT_ENTRY_16BIT_DS		6
19 #define X86_GDT_ENTRY_16BIT_FLAT_CS	7
20 #define X86_GDT_ENTRY_16BIT_FLAT_DS	8
21 #define X86_GDT_ENTRY_64BIT_CS		9
22 #define X86_GDT_ENTRY_64BIT_TS1		10
23 #define X86_GDT_ENTRY_64BIT_TS2		11
24 #define X86_GDT_NUM_ENTRIES		12
25 
26 #define X86_GDT_SIZE		(X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE)
27 
28 /* Length of the public header on Intel microcode blobs */
29 #define UCODE_HEADER_LEN	0x30
30 
31 /*
32  * This register is documented in (for example) the Intel Atom Processor E3800
33  * Product Family Datasheet in "PCU - Power Management Controller (PMC)".
34  *
35  * RST_CNT: Reset Control Register (RST_CNT) Offset cf9.
36  *
37  * The naming follows Intel's naming.
38  */
39 #define IO_PORT_RESET		0xcf9
40 
41 #define SYS_RST		(1 << 1)	/* 0 for soft reset, 1 for hard reset */
42 #define RST_CPU		(1 << 2)	/* initiate reset */
43 #define FULL_RST	(1 << 3)	/* full power cycle */
44 
45 #ifndef __ASSEMBLY__
46 
cpu_hlt(void)47 static inline __attribute__((always_inline)) void cpu_hlt(void)
48 {
49 	asm("hlt");
50 }
51 
cpu_get_sp(void)52 static inline ulong cpu_get_sp(void)
53 {
54 	ulong result;
55 
56 	asm volatile(
57 		"mov %%esp, %%eax"
58 		: "=a" (result));
59 	return result;
60 }
61 
62 #endif /* __ASSEMBLY__ */
63 
64 #endif
65