1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6 #define LOG_CATEGORY UCLASS_VIDEO
7
8 #include <dm.h>
9 #include <init.h>
10 #include <log.h>
11 #include <vesa.h>
12 #include <video.h>
13 #include <acpi/acpi_table.h>
14 #include <asm/fsp/fsp_support.h>
15 #include <asm/global_data.h>
16 #include <asm/intel_opregion.h>
17 #include <asm/mtrr.h>
18 #include <dm/acpi.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 struct pixel {
23 u8 pos;
24 u8 size;
25 };
26
27 static const struct fsp_framebuffer {
28 struct pixel red;
29 struct pixel green;
30 struct pixel blue;
31 struct pixel rsvd;
32 } fsp_framebuffer_format_map[] = {
33 [pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} },
34 [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} },
35 };
36
save_vesa_mode(struct vesa_mode_info * vesa)37 static int save_vesa_mode(struct vesa_mode_info *vesa)
38 {
39 const struct hob_graphics_info *ginfo;
40 const struct fsp_framebuffer *fbinfo;
41
42 ginfo = fsp_get_graphics_info(gd->arch.hob_list, NULL);
43
44 /*
45 * If there is no graphics info structure, bail out and keep
46 * running on the serial console.
47 *
48 * Note: on some platforms (eg: Braswell), the FSP will not produce
49 * the graphics info HOB unless you plug some cables to the display
50 * interface (eg: HDMI) on the board.
51 */
52 if (!ginfo) {
53 debug("FSP graphics hand-off block not found\n");
54 return -ENXIO;
55 }
56
57 vesa->x_resolution = ginfo->width;
58 vesa->y_resolution = ginfo->height;
59 vesa->bits_per_pixel = 32;
60 vesa->bytes_per_scanline = ginfo->pixels_per_scanline * 4;
61 vesa->phys_base_ptr = ginfo->fb_base;
62
63 if (ginfo->pixel_format >= pixel_bitmask) {
64 debug("FSP set unknown framebuffer format: %d\n",
65 ginfo->pixel_format);
66 return -EINVAL;
67 }
68 fbinfo = &fsp_framebuffer_format_map[ginfo->pixel_format];
69 vesa->red_mask_size = fbinfo->red.size;
70 vesa->red_mask_pos = fbinfo->red.pos;
71 vesa->green_mask_size = fbinfo->green.size;
72 vesa->green_mask_pos = fbinfo->green.pos;
73 vesa->blue_mask_size = fbinfo->blue.size;
74 vesa->blue_mask_pos = fbinfo->blue.pos;
75 vesa->reserved_mask_size = fbinfo->rsvd.size;
76 vesa->reserved_mask_pos = fbinfo->rsvd.pos;
77
78 return 0;
79 }
80
fsp_video_probe(struct udevice * dev)81 static int fsp_video_probe(struct udevice *dev)
82 {
83 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
84 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
85 struct vesa_mode_info *vesa = &mode_info.vesa;
86 int ret;
87
88 if (!ll_boot_init())
89 return -ENODEV;
90
91 printf("Video: ");
92
93 /* Initialize vesa_mode_info structure */
94 ret = save_vesa_mode(vesa);
95 if (ret)
96 goto err;
97
98 /*
99 * The framebuffer base address in the FSP graphics info HOB reflects
100 * the value assigned by the FSP. After PCI enumeration the framebuffer
101 * base address may be relocated. Let's get the updated one from device.
102 *
103 * For IGD, it seems to be always on BAR2.
104 */
105 vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2);
106
107 ret = vesa_setup_video_priv(vesa, vesa->phys_base_ptr, uc_priv, plat);
108 if (ret)
109 goto err;
110
111 mtrr_set_next_var(MTRR_TYPE_WRCOMB, vesa->phys_base_ptr, 256 << 20);
112
113 printf("%dx%dx%d @ %x\n", uc_priv->xsize, uc_priv->ysize,
114 vesa->bits_per_pixel, vesa->phys_base_ptr);
115
116 return 0;
117
118 err:
119 printf("No video mode configured in FSP!\n");
120 return ret;
121 }
122
fsp_video_bind(struct udevice * dev)123 static int fsp_video_bind(struct udevice *dev)
124 {
125 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
126
127 /* Set the maximum supported resolution */
128 plat->size = 2560 * 1600 * 4;
129
130 return 0;
131 }
132
133 #ifdef CONFIG_INTEL_GMA_ACPI
fsp_video_acpi_write_tables(const struct udevice * dev,struct acpi_ctx * ctx)134 static int fsp_video_acpi_write_tables(const struct udevice *dev,
135 struct acpi_ctx *ctx)
136 {
137 struct igd_opregion *opregion;
138 int ret;
139
140 log_debug("ACPI: * IGD OpRegion\n");
141 opregion = (struct igd_opregion *)ctx->current;
142
143 ret = intel_gma_init_igd_opregion((struct udevice *)dev, opregion);
144 if (ret)
145 return ret;
146
147 acpi_inc_align(ctx, sizeof(struct igd_opregion));
148
149 return 0;
150 }
151 #endif
152
153 struct acpi_ops fsp_video_acpi_ops = {
154 #ifdef CONFIG_INTEL_GMA_ACPI
155 .write_tables = fsp_video_acpi_write_tables,
156 #endif
157 };
158
159 static const struct udevice_id fsp_video_ids[] = {
160 { .compatible = "fsp-fb" },
161 { }
162 };
163
164 U_BOOT_DRIVER(fsp_video) = {
165 .name = "fsp_video",
166 .id = UCLASS_VIDEO,
167 .of_match = fsp_video_ids,
168 .bind = fsp_video_bind,
169 .probe = fsp_video_probe,
170 .flags = DM_FLAG_PRE_RELOC,
171 ACPI_OPS_PTR(&fsp_video_acpi_ops)
172 };
173
174 static struct pci_device_id fsp_video_supported[] = {
175 { PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, 0xffff00) },
176 { },
177 };
178
179 U_BOOT_PCI_DEVICE(fsp_video, fsp_video_supported);
180