1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6 #include <dm.h>
7 #include <errno.h>
8 #include <init.h>
9 #include <log.h>
10 #include <malloc.h>
11 #include <rtc.h>
12 #include <acpi/acpi_s3.h>
13 #include <asm/cmos_layout.h>
14 #include <asm/early_cmos.h>
15 #include <asm/global_data.h>
16 #include <asm/io.h>
17 #include <asm/mrccache.h>
18 #include <asm/post.h>
19 #include <asm/processor.h>
20 #include <asm/fsp1/fsp_support.h>
21
22 DECLARE_GLOBAL_DATA_PTR;
23
fsp_prepare_mrc_cache(void)24 static void *fsp_prepare_mrc_cache(void)
25 {
26 struct mrc_data_container *cache;
27 struct mrc_region entry;
28 int ret;
29
30 ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
31 if (ret)
32 return NULL;
33
34 cache = mrccache_find_current(&entry);
35 if (!cache)
36 return NULL;
37
38 debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
39 cache->data, cache->data_size, cache->checksum);
40
41 return cache->data;
42 }
43
arch_fsp_init(void)44 int arch_fsp_init(void)
45 {
46 void *nvs;
47 int stack = CONFIG_FSP_TEMP_RAM_ADDR;
48 int boot_mode = BOOT_FULL_CONFIG;
49 int prev_sleep_state;
50
51 if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
52 prev_sleep_state = chipset_prev_sleep_state();
53 gd->arch.prev_sleep_state = prev_sleep_state;
54 }
55
56 if (!gd->arch.hob_list) {
57 if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE))
58 nvs = fsp_prepare_mrc_cache();
59 else
60 nvs = NULL;
61
62 if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) &&
63 prev_sleep_state == ACPI_S3) {
64 if (nvs == NULL) {
65 /* If waking from S3 and no cache then */
66 debug("No MRC cache found in S3 resume path\n");
67 post_code(POST_RESUME_FAILURE);
68 /* Clear Sleep Type */
69 chipset_clear_sleep_state();
70 /* Reboot */
71 debug("Rebooting..\n");
72 outb(SYS_RST | RST_CPU, IO_PORT_RESET);
73 /* Should not reach here.. */
74 panic("Reboot System");
75 }
76
77 /*
78 * DM is not available yet at this point, hence call
79 * CMOS access library which does not depend on DM.
80 */
81 stack = cmos_read32(CMOS_FSP_STACK_ADDR);
82 boot_mode = BOOT_ON_S3_RESUME;
83 }
84
85 /*
86 * The first time we enter here, call fsp_init().
87 * Note the execution does not return to this function,
88 * instead it jumps to fsp_continue().
89 */
90 fsp_init(stack, boot_mode, nvs);
91 } else {
92 /*
93 * The second time we enter here, adjust the size of malloc()
94 * pool before relocation. Given gd->malloc_base was adjusted
95 * after the call to board_init_f_init_reserve() in arch/x86/
96 * cpu/start.S, we should fix up gd->malloc_limit here.
97 */
98 gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN;
99 }
100
101 return 0;
102 }
103 EVENT_SPY_SIMPLE(EVT_FSP_INIT_F, arch_fsp_init);
104