1menu "Xtensa architecture"
2	depends on XTENSA
3
4config SYS_ARCH
5	default "xtensa"
6
7config SYS_CPU
8	string "Xtensa Core Variant"
9
10choice
11	prompt "Target select"
12
13config TARGET_XTFPGA
14	bool "Support XTFPGA"
15	select BOARD_POSTCLK_INIT
16
17config TARGET_QEMU_XTENSA
18	bool "Support QEMU Xtensa Virt Board"
19	select BOARD_LATE_INIT
20
21endchoice
22
23config SYS_ICACHE_OFF
24	bool "Do not enable icache"
25	help
26	  Do not enable instruction cache in U-Boot.
27
28config SPL_SYS_ICACHE_OFF
29	bool "Do not enable icache in SPL"
30	depends on SPL
31	default SYS_ICACHE_OFF
32	help
33	  Do not enable instruction cache in SPL.
34
35config SYS_DCACHE_OFF
36	bool "Do not enable dcache"
37	help
38	  Do not enable data cache in U-Boot.
39
40config SPL_SYS_DCACHE_OFF
41	bool "Do not enable dcache in SPL"
42	depends on SPL
43	default SYS_DCACHE_OFF
44	help
45	  Do not enable data cache in SPL.
46
47config XTENSA_SEMIHOSTING
48	bool "Support semihosting"
49	help
50	  Enable Xtensa semihosting debugging support.
51
52choice
53	prompt "Semihosting interface"
54	default XTENSA_SIMCALL_ISS
55	depends on XTENSA_SEMIHOSTING
56	help
57	  Choose semihosting interface that will be used for serial port,
58	  block device and networking.
59
60config XTENSA_SIMCALL_ISS
61	bool "simcall"
62	help
63	  Use simcall instruction. simcall is only available on simulators,
64	  it does nothing on hardware.
65
66config XTENSA_SIMCALL_GDBIO
67	bool "GDBIO"
68	help
69	  Use break instruction. It is available on real hardware when GDB
70	  is attached to it via JTAG.
71
72endchoice
73
74source "board/cadence/xtfpga/Kconfig"
75source "board/emulation/qemu-xtensa/Kconfig"
76
77endmenu
78