1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2008-2013 Tensilica Inc. 4 * Copyright (C) 2016 Cadence Design Systems Inc. 5 */ 6 7 #ifndef _XTENSA_ADDRSPACE_H 8 #define _XTENSA_ADDRSPACE_H 9 10 #include <config.h> 11 12 #include <asm/arch/core.h> 13 14 /* 15 * MMU Memory Map 16 * 17 * noMMU and v3 MMU have identity mapped address space on reset. 18 * V2 MMU: 19 * IO (uncached) f0000000..ffffffff -> f000000 20 * IO (cached) e0000000..efffffff -> f000000 21 * MEM (uncached) d8000000..dfffffff -> 0000000 22 * MEM (cached) d0000000..d7ffffff -> 0000000 23 * 24 * The actual location of memory and IO is the board property. 25 */ 26 27 #define IOADDR(x) (CFG_SYS_IO_BASE + (x)) 28 #define MEMADDR(x) (CFG_SYS_MEMORY_BASE + (x)) 29 #define PHYSADDR(x) ((x) - XCHAL_VECBASE_RESET_VADDR + \ 30 XCHAL_VECBASE_RESET_PADDR) 31 32 #endif /* _XTENSA_ADDRSPACE_H */ 33