1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2006 Tensilica Inc. 4 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. 5 */ 6 7 #ifndef _XTENSA_CACHEASM_H 8 #define _XTENSA_CACHEASM_H 9 10 #include <asm/cache.h> 11 #include <asm/asmmacro.h> 12 #include <linux/stringify.h> 13 14 #define PAGE_SIZE 4096 15 #define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS) 16 #define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS) 17 #define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH) 18 #define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH) 19 20 /* 21 * Define cache functions as macros here so that they can be used 22 * by the kernel and boot loader. We should consider moving them to a 23 * library that can be linked by both. 24 * 25 * Locking 26 * 27 * ___unlock_dcache_all 28 * ___unlock_icache_all 29 * 30 * Flush and invaldating 31 * 32 * ___flush_invalidate_dcache_{all|range|page} 33 * ___flush_dcache_{all|range|page} 34 * ___invalidate_dcache_{all|range|page} 35 * ___invalidate_icache_{all|range|page} 36 * 37 */ 38 39 .macro __loop_cache_all ar at insn size line_width 40 41 movi \ar, 0 42 43 __loopi \ar, \at, \size, (4 << (\line_width)) 44 45 \insn \ar, 0 << (\line_width) 46 \insn \ar, 1 << (\line_width) 47 \insn \ar, 2 << (\line_width) 48 \insn \ar, 3 << (\line_width) 49 50 __endla \ar, \at, 4 << (\line_width) 51 52 .endm 53 54 .macro __loop_cache_range ar as at insn line_width 55 56 extui \at, \ar, 0, \line_width 57 add \as, \as, \at 58 59 __loops \ar, \as, \at, \line_width 60 \insn \ar, 0 61 __endla \ar, \at, (1 << (\line_width)) 62 63 .endm 64 65 .macro __loop_cache_page ar at insn line_width 66 67 __loopi \ar, \at, PAGE_SIZE, 4 << (\line_width) 68 69 \insn \ar, 0 << (\line_width) 70 \insn \ar, 1 << (\line_width) 71 \insn \ar, 2 << (\line_width) 72 \insn \ar, 3 << (\line_width) 73 74 __endla \ar, \at, 4 << (\line_width) 75 76 .endm 77 78 .macro ___unlock_dcache_all ar at 79 80 #if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE 81 __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH 82 #endif 83 84 .endm 85 86 .macro ___unlock_icache_all ar at 87 88 #if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE 89 __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH 90 #endif 91 92 .endm 93 94 .macro ___flush_invalidate_dcache_all ar at 95 96 #if XCHAL_DCACHE_SIZE 97 __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH 98 #endif 99 100 .endm 101 102 .macro ___flush_dcache_all ar at 103 104 #if XCHAL_DCACHE_SIZE 105 __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH 106 #endif 107 108 .endm 109 110 .macro ___invalidate_dcache_all ar at 111 112 #if XCHAL_DCACHE_SIZE 113 __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \ 114 XCHAL_DCACHE_LINEWIDTH 115 #endif 116 117 .endm 118 119 .macro ___invalidate_icache_all ar at 120 121 #if XCHAL_ICACHE_SIZE 122 __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \ 123 XCHAL_ICACHE_LINEWIDTH 124 #endif 125 126 .endm 127 128 .macro ___flush_invalidate_dcache_range ar as at 129 130 #if XCHAL_DCACHE_SIZE 131 __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH 132 #endif 133 134 .endm 135 136 .macro ___flush_dcache_range ar as at 137 138 #if XCHAL_DCACHE_SIZE 139 __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH 140 #endif 141 142 .endm 143 144 .macro ___invalidate_dcache_range ar as at 145 146 #if XCHAL_DCACHE_SIZE 147 __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH 148 #endif 149 150 .endm 151 152 .macro ___invalidate_icache_range ar as at 153 154 #if XCHAL_ICACHE_SIZE 155 __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH 156 #endif 157 158 .endm 159 160 .macro ___flush_invalidate_dcache_page ar as 161 162 #if XCHAL_DCACHE_SIZE 163 __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH 164 #endif 165 166 .endm 167 168 .macro ___flush_dcache_page ar as 169 170 #if XCHAL_DCACHE_SIZE 171 __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH 172 #endif 173 174 .endm 175 176 .macro ___invalidate_dcache_page ar as 177 178 #if XCHAL_DCACHE_SIZE 179 __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH 180 #endif 181 182 .endm 183 184 .macro ___invalidate_icache_page ar as 185 186 #if XCHAL_ICACHE_SIZE 187 __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH 188 #endif 189 190 .endm 191 192 #endif /* _XTENSA_CACHEASM_H */ 193