1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2024 Marek Behún <kabel@kernel.org>
4 */
5
6 #include <asm/arch/soc.h>
7 #include <asm/io.h>
8
9 #include "../drivers/ddr/marvell/a38x/old/ddr3_init.h"
10
11 static struct hws_topology_map board_topology_map_1g = {
12 0x1, /* active interfaces */
13 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
14 { { { {0x1, 0, 0, 0},
15 {0x1, 0, 0, 0},
16 {0x1, 0, 0, 0},
17 {0x1, 0, 0, 0},
18 {0x1, 0, 0, 0} },
19 SPEED_BIN_DDR_1600K, /* speed_bin */
20 BUS_WIDTH_16, /* memory_width */
21 MEM_4G, /* mem_size */
22 DDR_FREQ_800, /* frequency */
23 0, 0, /* cas_l cas_wl */
24 HWS_TEMP_NORMAL, /* temperature */
25 HWS_TIM_2T} }, /* timing (force 2t) */
26 5, /* Num Of Bus Per Interface*/
27 BUS_MASK_32BIT /* Busses mask */
28 };
29
30 static struct hws_topology_map board_topology_map_2g = {
31 0x1, /* active interfaces */
32 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
33 { { { {0x1, 0, 0, 0},
34 {0x1, 0, 0, 0},
35 {0x1, 0, 0, 0},
36 {0x1, 0, 0, 0},
37 {0x1, 0, 0, 0} },
38 SPEED_BIN_DDR_1600K, /* speed_bin */
39 BUS_WIDTH_16, /* memory_width */
40 MEM_8G, /* mem_size */
41 DDR_FREQ_800, /* frequency */
42 0, 0, /* cas_l cas_wl */
43 HWS_TEMP_NORMAL, /* temperature */
44 HWS_TIM_2T} }, /* timing (force 2t) */
45 5, /* Num Of Bus Per Interface*/
46 BUS_MASK_32BIT /* Busses mask */
47 };
48
49 /* defined in turris_omnia.c */
50 extern int omnia_get_ram_size_gb(void);
51
ddr3_get_topology_map(void)52 struct hws_topology_map *ddr3_get_topology_map(void)
53 {
54 if (omnia_get_ram_size_gb() == 2)
55 return &board_topology_map_2g;
56 else
57 return &board_topology_map_1g;
58 }
59
sys_env_get_topology_update_info(struct topology_update_info * tui)60 __weak u32 sys_env_get_topology_update_info(struct topology_update_info *tui)
61 {
62 return MV_OK;
63 }
64