1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 */
5
6 #include <init.h>
7 #include <miiphy.h>
8 #include <net.h>
9 #include <netdev.h>
10 #include <asm/global_data.h>
11 #include <asm/io.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
14 #include <linux/bitops.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 #define ETH_PHY_CTRL_REG 0
19 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11
20 #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
21
22 /*
23 * Those values and defines are taken from the Marvell U-Boot version
24 * "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka
25 * "RD-AXP-GP rev 1.0".
26 *
27 * GPPs
28 * MPP# NAME IN/OUT
29 * ----------------------------------------------
30 * 21 SW_Reset_ OUT
31 * 25 Phy_Int# IN
32 * 28 SDI_WP IN
33 * 29 SDI_Status IN
34 * 54-61 On GPP Connector ?
35 * 62 Switch Interrupt IN
36 * 63-65 Reserved from SW Board ?
37 * 66 SW_BRD connected IN
38 */
39 #define RD_78460_GP_GPP_OUT_ENA_LOW (~(BIT(21) | BIT(20)))
40 #define RD_78460_GP_GPP_OUT_ENA_MID (~(BIT(26) | BIT(27)))
41 #define RD_78460_GP_GPP_OUT_ENA_HIGH (~(0x0))
42
43 #define RD_78460_GP_GPP_OUT_VAL_LOW (BIT(21) | BIT(20))
44 #define RD_78460_GP_GPP_OUT_VAL_MID (BIT(26) | BIT(27))
45 #define RD_78460_GP_GPP_OUT_VAL_HIGH 0x0
46
board_early_init_f(void)47 int board_early_init_f(void)
48 {
49 /* Configure MPP */
50 writel(0x00000000, MVEBU_MPP_BASE + 0x00);
51 writel(0x00000000, MVEBU_MPP_BASE + 0x04);
52 writel(0x33000000, MVEBU_MPP_BASE + 0x08);
53 writel(0x11000000, MVEBU_MPP_BASE + 0x0c);
54 writel(0x11111111, MVEBU_MPP_BASE + 0x10);
55 writel(0x00221100, MVEBU_MPP_BASE + 0x14);
56 writel(0x00000003, MVEBU_MPP_BASE + 0x18);
57 writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
58 writel(0x00000000, MVEBU_MPP_BASE + 0x20);
59
60 /* Configure GPIO */
61 writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
62 writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
63 writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
64 writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
65 writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
66 writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
67
68 return 0;
69 }
70
board_init(void)71 int board_init(void)
72 {
73 /* adress of boot parameters */
74 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
75
76 return 0;
77 }
78
checkboard(void)79 int checkboard(void)
80 {
81 puts("Board: Marvell DB-MV784MP-GP\n");
82
83 return 0;
84 }
85
board_eth_init(struct bd_info * bis)86 int board_eth_init(struct bd_info *bis)
87 {
88 cpu_eth_init(bis); /* Built in controller(s) come first */
89 return pci_eth_init(bis);
90 }
91
board_phy_config(struct phy_device * phydev)92 int board_phy_config(struct phy_device *phydev)
93 {
94 u16 reg;
95
96 /* Enable QSGMII AN */
97 /* Set page to 4 */
98 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4);
99 /* Enable AN */
100 phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140);
101 /* Set page to 0 */
102 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0);
103
104 /* Phy C_ANEG */
105 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4);
106 reg |= 0x1E0;
107 phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg);
108
109 /* Soft-Reset */
110 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
111 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
112
113 /* Power up the phy */
114 reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG);
115 reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
116 phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg);
117
118 printf("88E1545 Initialized\n");
119 return 0;
120 }
121