1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2019 NXP
4 * Copyright 2022 Linaro
5 */
6
7 #include <dwc3-uboot.h>
8 #include <efi.h>
9 #include <efi_loader.h>
10 #include <env.h>
11 #include <errno.h>
12 #include <miiphy.h>
13 #include <netdev.h>
14 #include <spl.h>
15 #include <usb.h>
16 #include <asm/io.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm-generic/gpio.h>
19 #include <asm/arch/imx8mp_pins.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/mach-imx/gpio.h>
22 #include <asm/mach-imx/mxc_i2c.h>
23 #include <asm/arch/clock.h>
24 #include <asm/mach-imx/dma.h>
25 #include <linux/delay.h>
26 #include <linux/kernel.h>
27 #include <power/pmic.h>
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 #ifdef CONFIG_NAND_MXS
setup_gpmi_nand(void)32 static void setup_gpmi_nand(void)
33 {
34 init_nand_clk();
35 }
36 #endif
37
38 #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
39 struct efi_fw_image fw_images[] = {
40 #if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_4G)
41 {
42 .image_type_id = IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID,
43 .fw_name = u"IMX8MP-RSB3720-FIT",
44 .image_index = 1,
45 },
46 #elif defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G)
47 {
48 .image_type_id = IMX8MP_RSB3720A1_6G_FIT_IMAGE_GUID,
49 .fw_name = u"IMX8MP-RSB3720-FIT",
50 .image_index = 1,
51 },
52 #endif
53 };
54
55 struct efi_capsule_update_info update_info = {
56 .dfu_string = "mmc 2=flash-bin raw 0 0x1B00 mmcpart 1",
57 .num_images = ARRAY_SIZE(fw_images),
58 .images = fw_images,
59 };
60
61 #endif /* EFI_HAVE_CAPSULE_SUPPORT */
62
board_early_init_f(void)63 int board_early_init_f(void)
64 {
65 init_uart_clk(2);
66
67 return 0;
68 }
69
70 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,struct bd_info * bd)71 int ft_board_setup(void *blob, struct bd_info *bd)
72 {
73 return 0;
74 }
75 #endif
76
77 #ifdef CONFIG_FEC_MXC
78 #define FEC_RST_PAD IMX_GPIO_NR(4, 2)
79 static const iomux_v3_cfg_t fec1_rst_pads[] = {
80 MX8MP_PAD_SAI1_RXD0__GPIO4_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
81 };
82
setup_iomux_fec(void)83 static void setup_iomux_fec(void)
84 {
85 imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
86 ARRAY_SIZE(fec1_rst_pads));
87
88 gpio_request(FEC_RST_PAD, "fec1_rst");
89 gpio_direction_output(FEC_RST_PAD, 0);
90 mdelay(15);
91 gpio_direction_output(FEC_RST_PAD, 1);
92 mdelay(100);
93 }
94
setup_fec(void)95 static int setup_fec(void)
96 {
97 struct iomuxc_gpr_base_regs *gpr =
98 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
99
100 setup_iomux_fec();
101
102 /* Enable RGMII TX clk output */
103 setbits_le32(&gpr->gpr[1], BIT(22));
104
105 return 0;
106 }
107 #endif /* CONFIG_FEC_MXC */
108
109 #ifdef CONFIG_DWC_ETH_QOS
110 #define EQOS_RST_PAD IMX_GPIO_NR(4, 22)
111 static const iomux_v3_cfg_t eqos_rst_pads[] = {
112 MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
113 };
114
setup_eqos(void)115 static void setup_eqos(void)
116 {
117 imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
118 ARRAY_SIZE(eqos_rst_pads));
119
120 gpio_request(EQOS_RST_PAD, "eqos_rst");
121 gpio_direction_output(EQOS_RST_PAD, 0);
122 mdelay(15);
123 gpio_direction_output(EQOS_RST_PAD, 1);
124 mdelay(100);
125 }
126 #endif /* CONFIG_DWC_ETH_QOS */
127
board_phy_config(struct phy_device * phydev)128 int board_phy_config(struct phy_device *phydev)
129 {
130 if (IS_ENABLED(CONFIG_FEC_MXC) || IS_ENABLED(CONFIG_DWC_ETH_QOS)) {
131 /* enable rgmii rxc skew and phy mode select to RGMII copper */
132 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
133 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
134
135 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
136 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
137 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
138 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
139
140 if (phydev->drv->config)
141 phydev->drv->config(phydev);
142 }
143
144 return 0;
145 }
146
147 #define DISPMIX 13
148 #define MIPI 15
149
150 #define WDOG_TRIG IMX_GPIO_NR(4, 20)
151
152 static iomux_v3_cfg_t wdt_trig[] = {
153 MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
154 };
155
setup_iomux_wdt(void)156 static void setup_iomux_wdt(void)
157 {
158 imx_iomux_v3_setup_multiple_pads(wdt_trig, ARRAY_SIZE(wdt_trig));
159 gpio_request(WDOG_TRIG, "wdt_trig");
160 gpio_direction_output(WDOG_TRIG, 1);
161 }
162
board_init(void)163 int board_init(void)
164 {
165 #ifdef CONFIG_FEC_MXC
166 setup_fec();
167 #endif
168
169 #ifdef CONFIG_DWC_ETH_QOS
170 /* clock, pin, gpr */
171 setup_eqos();
172 #endif
173
174 #ifdef CONFIG_NAND_MXS
175 setup_gpmi_nand();
176 #endif
177
178 setup_iomux_wdt();
179
180 return 0;
181 }
182
board_late_init(void)183 int board_late_init(void)
184 {
185 if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
186 env_set("board_name", "RSB3720A1");
187 env_set("board_rev", "iMX8MP");
188 }
189
190 return 0;
191 }
192
193 #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
194 #define UBOOT_RAW_SECTOR_OFFSET 0x40
board_spl_mmc_get_uboot_raw_sector(struct mmc * mmc,unsigned long raw_sector)195 unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
196 unsigned long raw_sector)
197 {
198 u32 boot_dev = spl_boot_device();
199
200 switch (boot_dev) {
201 case BOOT_DEVICE_MMC2:
202 return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET;
203 default:
204 return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
205 }
206 }
207 #endif /* CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR */
208