1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2020 Arm Limited
4  * Usama Arif <usama.arif@arm.com>
5  */
6 
7 #include <config.h>
8 #include <dm.h>
9 #include <dm/platform_data/serial_pl01x.h>
10 #include <cpu_func.h>
11 #include <env.h>
12 #include <linux/sizes.h>
13 
14 #include <asm/armv8/mmu.h>
15 #include <asm/global_data.h>
16 #include <asm/system.h>
17 
18 /* +1 is end of list which needs to be empty */
19 #define TC_MEM_MAP_MAX		(1 + CONFIG_NR_DRAM_BANKS + 1)
20 
21 static struct mm_region total_compute_mem_map[TC_MEM_MAP_MAX] = {
22 	{
23 		.virt = 0x0UL,
24 		.phys = 0x0UL,
25 		.size = 0x80000000UL,
26 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
27 			 PTE_BLOCK_NON_SHARE |
28 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
29 	}
30 };
31 
32 struct mm_region *mem_map = total_compute_mem_map;
33 
34 #ifdef CONFIG_OF_HAS_PRIOR_STAGE
35 /*
36  * Push the variable into the .data section so that it
37  * does not get cleared later.
38  */
39 unsigned long __section(".data") fw_dtb_pointer;
40 
board_fdt_blob_setup(void ** fdtp)41 int board_fdt_blob_setup(void **fdtp)
42 {
43 	if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC)
44 		return -ENXIO;
45 
46 	*fdtp = (void *)fw_dtb_pointer;
47 	return 0;
48 }
49 #endif
50 
misc_init_r(void)51 int misc_init_r(void)
52 {
53 	size_t base;
54 
55 #ifdef CONFIG_OF_HAS_PRIOR_STAGE
56 	if (!env_get("fdt_addr_r"))
57 		env_set_hex("fdt_addr_r", fw_dtb_pointer);
58 #endif
59 	if (!env_get("kernel_addr_r")) {
60 		/*
61 		 * The kernel has to be 2M aligned and the first 64K at the
62 		 * start of SDRAM is reserved for DTB.
63 		 */
64 		base = gd->ram_base + SZ_2M;
65 		assert(IS_ALIGNED(base, SZ_2M));
66 
67 		env_set_hex("kernel_addr_r", base);
68 	}
69 
70 	return 0;
71 }
72 
dram_init(void)73 int dram_init(void)
74 {
75 	return fdtdec_setup_mem_size_base();
76 }
77 
dram_init_banksize(void)78 int dram_init_banksize(void)
79 {
80 	return fdtdec_setup_memory_banksize();
81 }
82 
build_mem_map(void)83 void build_mem_map(void)
84 {
85 	int i;
86 
87 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
88 		/*
89 		 * The first node is for I/O device, start from node 1 for
90 		 * updating DRAM info.
91 		 */
92 		mem_map[i + 1].virt = gd->bd->bi_dram[i].start;
93 		mem_map[i + 1].phys = gd->bd->bi_dram[i].start;
94 		mem_map[i + 1].size = gd->bd->bi_dram[i].size;
95 		mem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
96 				       PTE_BLOCK_INNER_SHARE;
97 	}
98 }
99 
enable_caches(void)100 void enable_caches(void)
101 {
102 	build_mem_map();
103 
104 	icache_enable();
105 	dcache_enable();
106 }
107 
get_page_table_size(void)108 u64 get_page_table_size(void)
109 {
110 	return SZ_256K;
111 }
112 
113 /* Nothing to be done here as handled by PSCI interface */
reset_cpu(void)114 void reset_cpu(void)
115 {
116 }
117