1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2013
4 * David Feng <fenghua@phytium.com.cn>
5 * Sharma Bhupesh <bhupesh.sharma@freescale.com>
6 */
7 #include <config.h>
8 #include <cpu_func.h>
9 #include <dm.h>
10 #include <init.h>
11 #include <malloc.h>
12 #include <errno.h>
13 #include <net.h>
14 #include <netdev.h>
15 #include <asm/global_data.h>
16 #include <asm/io.h>
17 #include <linux/compiler.h>
18 #include <linux/sizes.h>
19 #include <dm/platform_data/serial_pl01x.h>
20 #include "pcie.h"
21 #include <asm/armv8/mmu.h>
22 #ifdef CONFIG_VIRTIO_NET
23 #include <virtio_types.h>
24 #include <virtio.h>
25 #endif
26
27 DECLARE_GLOBAL_DATA_PTR;
28
29 static const struct pl01x_serial_plat serial_plat = {
30 .base = V2M_UART0,
31 .type = TYPE_PL011,
32 .clock = CFG_PL011_CLOCK,
33 };
34
35 U_BOOT_DRVINFO(vexpress_serials) = {
36 .name = "serial_pl01x",
37 .plat = &serial_plat,
38 };
39
40 static struct mm_region vexpress64_mem_map[] = {
41 {
42 .virt = V2M_PA_BASE,
43 .phys = V2M_PA_BASE,
44 .size = SZ_2G,
45 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
46 PTE_BLOCK_NON_SHARE |
47 PTE_BLOCK_PXN | PTE_BLOCK_UXN
48 }, {
49 .virt = V2M_DRAM_BASE,
50 .phys = V2M_DRAM_BASE,
51 .size = SZ_2G,
52 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
53 PTE_BLOCK_INNER_SHARE
54 }, {
55 /*
56 * DRAM beyond 2 GiB is located high. Let's map just some
57 * of it, although U-Boot won't realistically use it, and
58 * the actual available amount might be smaller on the model.
59 */
60 .virt = 0x880000000UL, /* 32 + 2 GiB */
61 .phys = 0x880000000UL,
62 .size = 6UL * SZ_1G,
63 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
64 PTE_BLOCK_INNER_SHARE
65 }, {
66 /* List terminator */
67 0,
68 }
69 };
70
71 struct mm_region *mem_map = vexpress64_mem_map;
72
73 /* This function gets replaced by platforms supporting PCIe.
74 * The replacement function, eg. on Juno, initialises the PCIe bus.
75 */
vexpress64_pcie_init(void)76 __weak void vexpress64_pcie_init(void)
77 {
78 }
79
board_init(void)80 int board_init(void)
81 {
82 vexpress64_pcie_init();
83 #ifdef CONFIG_VIRTIO_NET
84 virtio_init();
85 #endif
86 return 0;
87 }
88
dram_init(void)89 int dram_init(void)
90 {
91 return fdtdec_setup_mem_size_base();
92 }
93
dram_init_banksize(void)94 int dram_init_banksize(void)
95 {
96 return fdtdec_setup_memory_banksize();
97 }
98
99 /* Assigned in lowlevel_init.S
100 * Push the variable into the .data section so that it
101 * does not get cleared later.
102 */
103 #ifdef CONFIG_OF_HAS_PRIOR_STAGE
104 unsigned long __section(".data") prior_stage_fdt_address[2];
105 #endif
106
107 #ifdef CONFIG_OF_BOARD
108
109 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
110 #define JUNO_FLASH_SEC_SIZE (256 * 1024)
find_dtb_in_nor_flash(const char * partname)111 static phys_addr_t find_dtb_in_nor_flash(const char *partname)
112 {
113 phys_addr_t sector = CFG_SYS_FLASH_BASE;
114 int i;
115
116 for (i = 0;
117 i < CONFIG_SYS_MAX_FLASH_SECT;
118 i++, sector += JUNO_FLASH_SEC_SIZE) {
119 int len = strlen(partname) + 1;
120 int offs;
121 phys_addr_t imginfo;
122 u32 reg;
123
124 reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x04);
125 /* This makes up the string "HSLFTOOF" flash footer */
126 if (reg != 0x464F4F54U)
127 continue;
128 reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x08);
129 if (reg != 0x464C5348U)
130 continue;
131
132 for (offs = 0; offs < 32; offs += 4, len -= 4) {
133 reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x30 + offs);
134 if (strncmp(partname + offs, (char *)®,
135 len > 4 ? 4 : len))
136 break;
137
138 if (len > 4)
139 continue;
140
141 reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x10);
142 imginfo = sector + JUNO_FLASH_SEC_SIZE - 0x30 - reg;
143 reg = readl(imginfo + 0x54);
144
145 return CFG_SYS_FLASH_BASE +
146 reg * JUNO_FLASH_SEC_SIZE;
147 }
148 }
149
150 printf("No DTB found\n");
151
152 return ~0;
153 }
154 #endif
155
156 #ifdef CONFIG_OF_HAS_PRIOR_STAGE
157 /*
158 * Filter for a valid DTB, as TF-A happens to provide a pointer to some
159 * data structure using the DTB format, which we cannot use.
160 * The address of the DTB cannot be 0, in fact this is the reserved value
161 * for x1 in the kernel boot protocol.
162 * And while the nt_fw_config.dtb used by TF-A is a valid DTB structure, it
163 * does not contain the typical nodes and properties, which we test for by
164 * probing for the mandatory /memory node.
165 */
is_valid_dtb(uintptr_t dtb_ptr)166 static bool is_valid_dtb(uintptr_t dtb_ptr)
167 {
168 if (dtb_ptr == 0 || fdt_magic(dtb_ptr) != FDT_MAGIC)
169 return false;
170
171 return fdt_subnode_offset((void *)dtb_ptr, 0, "memory") >= 0;
172 }
173
board_fdt_blob_setup(void ** fdtp)174 int board_fdt_blob_setup(void **fdtp)
175 {
176 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
177 phys_addr_t fdt_rom_addr = find_dtb_in_nor_flash(CONFIG_JUNO_DTB_PART);
178
179 if (fdt_rom_addr == ~0UL)
180 return -ENXIO;
181
182 *fdtp = (void *)fdt_rom_addr;
183 return 0;
184 #endif
185
186 #ifdef VEXPRESS_FDT_ADDR
187 if (fdt_magic(VEXPRESS_FDT_ADDR) == FDT_MAGIC) {
188 *fdtp = (void *)VEXPRESS_FDT_ADDR;
189 return 0;
190 }
191 #endif
192
193 if (is_valid_dtb(prior_stage_fdt_address[1])) {
194 *fdtp = (void *)prior_stage_fdt_address[1];
195 return 0;
196 } else if (is_valid_dtb(prior_stage_fdt_address[0])) {
197 *fdtp = (void *)prior_stage_fdt_address[0];
198 return 0;
199 }
200
201 if (fdt_magic(*fdtp) == FDT_MAGIC)
202 return 0;
203
204 return -ENXIO;
205 }
206 #endif
207 #endif
208
209 /* Actual reset is done via PSCI. */
reset_cpu(void)210 void reset_cpu(void)
211 {
212 }
213
214 /*
215 * Board specific ethernet initialization routine.
216 */
board_eth_init(struct bd_info * bis)217 int board_eth_init(struct bd_info *bis)
218 {
219 int rc = 0;
220 #ifndef CONFIG_DM_ETH
221 #ifdef CONFIG_SMC911X
222 rc = smc911x_initialize(0, CFG_SMC911X_BASE);
223 #endif
224 #endif
225 return rc;
226 }
227