1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2022 Logic PD, Inc dba Beacon EmbeddedWorks
4 *
5 */
6
7 #include <hang.h>
8 #include <init.h>
9 #include <log.h>
10 #include <spl.h>
11 #include <asm/global_data.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/imx8mp_pins.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/mach-imx/boot_mode.h>
16 #include <asm/mach-imx/gpio.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <asm/arch/ddr.h>
20 #include <power/pmic.h>
21 #include <power/pca9450.h>
22 #include <dm/uclass.h>
23 #include <dm/device.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
spl_board_boot_device(enum boot_device boot_dev_spl)27 int spl_board_boot_device(enum boot_device boot_dev_spl)
28 {
29 return BOOT_DEVICE_BOOTROM;
30 }
31
spl_dram_init(void)32 void spl_dram_init(void)
33 {
34 ddr_init(&dram_timing);
35 }
36
spl_board_init(void)37 void spl_board_init(void)
38 {
39 if (IS_ENABLED(CONFIG_FSL_CAAM)) {
40 struct udevice *dev;
41 int ret;
42
43 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
44 if (ret)
45 printf("Failed to initialize caam_jr: %d\n", ret);
46 }
47 /*
48 * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
49 * not allow to change it. Should set the clock after PMIC
50 * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
51 * set by ROM for ND VDD_SOC
52 */
53 if (!IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) {
54 clock_enable(CCGR_GIC, 0);
55 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
56 clock_enable(CCGR_GIC, 1);
57 }
58 }
59
60 #if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
power_init_board(void)61 int power_init_board(void)
62 {
63 struct udevice *dev;
64 int ret;
65
66 ret = pmic_get("pmic@25", &dev);
67 if (ret == -ENODEV) {
68 puts("No pmic@25\n");
69 return 0;
70 }
71 if (ret != 0)
72 return ret;
73
74 /* BUCKxOUT_DVS0/1 control BUCK123 output */
75 pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
76
77 /*
78 * increase VDD_SOC to typical value 0.95V before first
79 * DRAM access, set DVS1 to 0.85v for suspend.
80 * Enable DVS control through PMIC_STBY_REQ and
81 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
82 */
83 if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV))
84 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
85 else
86 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
87
88 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
89 pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
90
91 /* Kernel uses OD/OD freq for SOC */
92 /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
93 pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
94
95 return 0;
96 }
97 #endif
98
99 #if IS_ENABLED(CONFIG_SPL_LOAD_FIT)
board_fit_config_name_match(const char * name)100 int board_fit_config_name_match(const char *name)
101 {
102 /* Just empty function now - can't decide what to choose */
103 debug("%s: %s\n", __func__, name);
104
105 return 0;
106 }
107 #endif
108
board_init_f(ulong dummy)109 void board_init_f(ulong dummy)
110 {
111 int ret;
112
113 arch_cpu_init();
114
115 ret = spl_early_init();
116 if (ret) {
117 debug("spl_init() failed: %d\n", ret);
118 hang();
119 }
120
121 preloader_console_init();
122
123 enable_tzc380();
124
125 power_init_board();
126
127 /* DDR initialization */
128 spl_dram_init();
129 }
130