1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * https://beagleplay.org/
4 *
5 * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
6 * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
7 */
8
9 #include <efi_loader.h>
10 #include <cpu_func.h>
11 #include <env.h>
12 #include <fdt_support.h>
13 #include <spl.h>
14
15 #include <asm/arch/hardware.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 struct efi_fw_image fw_images[] = {
20 {
21 .image_type_id = BEAGLEPLAY_TIBOOT3_IMAGE_GUID,
22 .fw_name = u"BEAGLEPLAY_TIBOOT3",
23 .image_index = 1,
24 },
25 {
26 .image_type_id = BEAGLEPLAY_SPL_IMAGE_GUID,
27 .fw_name = u"BEAGLEPLAY_SPL",
28 .image_index = 2,
29 },
30 {
31 .image_type_id = BEAGLEPLAY_UBOOT_IMAGE_GUID,
32 .fw_name = u"BEAGLEPLAY_UBOOT",
33 .image_index = 3,
34 }
35 };
36
37 struct efi_capsule_update_info update_info = {
38 .dfu_string = "mmc 0=tiboot3.bin raw 0 2000 mmcpart 1;"
39 "tispl.bin fat 0 1;u-boot.img fat 0 1",
40 .num_images = ARRAY_SIZE(fw_images),
41 .images = fw_images,
42 };
43
dram_init(void)44 int dram_init(void)
45 {
46 return fdtdec_setup_mem_size_base();
47 }
48
dram_init_banksize(void)49 int dram_init_banksize(void)
50 {
51 return fdtdec_setup_memory_banksize();
52 }
53
54 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)55 int board_late_init(void)
56 {
57 char fdtfile[50];
58
59 snprintf(fdtfile, sizeof(fdtfile), "%s.dtb", CONFIG_DEFAULT_DEVICE_TREE);
60
61 env_set("fdtfile", fdtfile);
62
63 return 0;
64 }
65 #endif
66
67 #ifdef CONFIG_SPL_BOARD_INIT
68
69 /*
70 * Enable the 32k Crystal: needed for accurate 32k clock
71 * and external clock sources such as wlan 32k input clock
72 * supplied from the SoC to the wlan chip.
73 *
74 * The trim setup can be very highly board type specific choice of the crystal
75 * So this is done in the board file, though, in this case, no specific trim
76 * is necessary.
77 */
crystal_32k_enable(void)78 static void crystal_32k_enable(void)
79 {
80 /* Only mess with 32k at the start of boot from R5 */
81 if (IS_ENABLED(CONFIG_CPU_V7R)) {
82 /*
83 * We have external 32k crystal, so lets enable it (0x0)
84 * and disable bypass (0x0)
85 */
86 writel(0x0, MCU_CTRL_LFXOSC_CTRL);
87
88 /* Add any crystal specific TRIM needed here.. */
89
90 /* Make sure to mux the SoC 32k from the crystal */
91 writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL,
92 MCU_CTRL_DEVICE_CLKOUT_32K_CTRL);
93 }
94 }
95
debounce_configure(void)96 static void debounce_configure(void)
97 {
98 /* Configure debounce one time from R5 */
99 if (IS_ENABLED(CONFIG_CPU_V7R)) {
100 /*
101 * Setup debounce time registers.
102 * arbitrary values. Times are approx
103 */
104 /* 1.9ms debounce @ 32k */
105 writel(0x1, CTRLMMR_DBOUNCE_CFG(1));
106 /* 5ms debounce @ 32k */
107 writel(0x5, CTRLMMR_DBOUNCE_CFG(2));
108 /* 20ms debounce @ 32k */
109 writel(0x14, CTRLMMR_DBOUNCE_CFG(3));
110 /* 46ms debounce @ 32k */
111 writel(0x18, CTRLMMR_DBOUNCE_CFG(4));
112 /* 100ms debounce @ 32k */
113 writel(0x1c, CTRLMMR_DBOUNCE_CFG(5));
114 /* 156ms debounce @ 32k */
115 writel(0x1f, CTRLMMR_DBOUNCE_CFG(6));
116 }
117 }
118
spl_board_init(void)119 void spl_board_init(void)
120 {
121 crystal_32k_enable();
122 debounce_configure();
123 }
124 #endif
125