1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007 - 2013 Tensilica Inc.
4 * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
5 */
6
7 #include <config.h>
8 #include <clock_legacy.h>
9 #include <command.h>
10 #include <dm.h>
11 #include <init.h>
12 #include <dm/platform_data/net_ethoc.h>
13 #include <env.h>
14 #include <linux/ctype.h>
15 #include <linux/string.h>
16 #include <linux/stringify.h>
17 #include <asm/global_data.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 /*
22 * Check board idendity.
23 * (Print information about the board to stdout.)
24 */
25
26 #if defined(CONFIG_XTFPGA_LX60)
27 const char *board = "XT_AV60";
28 const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / ";
29 #elif defined(CONFIG_XTFPGA_LX110)
30 const char *board = "XT_AV110";
31 const char *description = "Avnet Xilinx Virtex-5 LX110 Evaluation Kit / ";
32 #elif defined(CONFIG_XTFPGA_LX200)
33 const char *board = "XT_AV200";
34 const char *description = "Avnet Xilinx Virtex-4 LX200 Evaluation Kit / ";
35 #elif defined(CONFIG_XTFPGA_ML605)
36 const char *board = "XT_ML605";
37 const char *description = "Xilinx Virtex-6 FPGA ML605 Evaluation Kit / ";
38 #elif defined(CONFIG_XTFPGA_KC705)
39 const char *board = "XT_KC705";
40 const char *description = "Xilinx Kintex-7 FPGA KC705 Evaluation Kit / ";
41 #else
42 const char *board = "<unknown>";
43 const char *description = "";
44 #endif
45
checkboard(void)46 int checkboard(void)
47 {
48 printf("Board: %s: %sTensilica bitstream\n", board, description);
49 return 0;
50 }
51
get_board_sys_clk(void)52 unsigned long get_board_sys_clk(void)
53 {
54 /*
55 * Obtain CPU clock frequency from board and cache in global
56 * data structure (Hz). Return 0 on success (OK to continue),
57 * else non-zero (hang).
58 */
59
60 #ifdef CFG_SYS_FPGAREG_FREQ
61 return (*(volatile unsigned long *)CFG_SYS_FPGAREG_FREQ);
62 #else
63 /* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
64 return 50000000;
65 #endif
66 }
67
dram_init(void)68 int dram_init(void)
69 {
70 return 0;
71 }
72
board_postclk_init(void)73 int board_postclk_init(void)
74 {
75 gd->cpu_clk = get_board_sys_clk();
76
77 return 0;
78 }
79
80 /*
81 * Miscellaneous late initializations.
82 * The environment has been set up, so we can set the Ethernet address.
83 */
84
misc_init_r(void)85 int misc_init_r(void)
86 {
87 #ifdef CONFIG_CMD_NET
88 /*
89 * Initialize ethernet environment variables and board info.
90 * Default MAC address comes from CONFIG_ETHADDR + DIP switches 1-6.
91 */
92
93 char *s = env_get("ethaddr");
94 if (s == 0) {
95 unsigned int x;
96 char s[] = __stringify(CFG_ETHBASE);
97 x = (*(volatile u32 *)CFG_SYS_FPGAREG_DIPSW)
98 & FPGAREG_MAC_MASK;
99 sprintf(&s[15], "%02x", x);
100 env_set("ethaddr", s);
101 }
102 #endif /* CONFIG_CMD_NET */
103
104 return 0;
105 }
106
107 U_BOOT_DRVINFO(sysreset) = {
108 .name = "xtfpga_sysreset",
109 };
110
111 static struct ethoc_eth_pdata ethoc_pdata = {
112 .eth_pdata = {
113 .iobase = CFG_SYS_ETHOC_BASE,
114 },
115 .packet_base = CFG_SYS_ETHOC_BUFFER_ADDR,
116 };
117
118 U_BOOT_DRVINFO(ethoc) = {
119 .name = "ethoc",
120 .plat = ðoc_pdata,
121 };
122