1 // SPDX-License-Identifier: GPL-2.0+
2 /**
3 * (C) Copyright 2014, Cavium Inc.
4 **/
5
6 #include <config.h>
7 #include <cpu_func.h>
8 #include <dm.h>
9 #include <init.h>
10 #include <malloc.h>
11 #include <errno.h>
12 #include <net.h>
13 #include <asm/global_data.h>
14 #include <linux/compiler.h>
15
16 #include <cavium/atf.h>
17 #include <asm/armv8/mmu.h>
18
19 #if !CONFIG_IS_ENABLED(OF_CONTROL)
20 #include <dm/platform_data/serial_pl01x.h>
21
22 static const struct pl01x_serial_plat serial0 = {
23 .base = CFG_SYS_SERIAL0,
24 .type = TYPE_PL011,
25 .clock = 0,
26 .skip_init = true,
27 };
28
29 U_BOOT_DRVINFO(thunderx_serial0) = {
30 .name = "serial_pl01x",
31 .plat = &serial0,
32 };
33
34 static const struct pl01x_serial_plat serial1 = {
35 .base = CFG_SYS_SERIAL1,
36 .type = TYPE_PL011,
37 .clock = 0,
38 .skip_init = true,
39 };
40
41 U_BOOT_DRVINFO(thunderx_serial1) = {
42 .name = "serial_pl01x",
43 .plat = &serial1,
44 };
45 #endif
46
47 DECLARE_GLOBAL_DATA_PTR;
48
49 static struct mm_region thunderx_mem_map[] = {
50 {
51 .virt = 0x000000000000UL,
52 .phys = 0x000000000000UL,
53 .size = 0x40000000000UL,
54 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE,
55 }, {
56 .virt = 0x800000000000UL,
57 .phys = 0x800000000000UL,
58 .size = 0x40000000000UL,
59 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
60 PTE_BLOCK_NON_SHARE,
61 }, {
62 .virt = 0x840000000000UL,
63 .phys = 0x840000000000UL,
64 .size = 0x40000000000UL,
65 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
66 PTE_BLOCK_NON_SHARE,
67 }, {
68 /* List terminator */
69 0,
70 }
71 };
72
73 struct mm_region *mem_map = thunderx_mem_map;
74
timer_init(void)75 int timer_init(void)
76 {
77 return 0;
78 }
79
dram_init(void)80 int dram_init(void)
81 {
82 ssize_t node_count = atf_node_count();
83 ssize_t dram_size;
84 int node;
85
86 printf("Initializing\nNodes in system: %zd\n", node_count);
87
88 gd->ram_size = 0;
89
90 for (node = 0; node < node_count; node++) {
91 dram_size = atf_dram_size(node);
92 printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20);
93 gd->ram_size += dram_size;
94 }
95
96 gd->ram_size -= MEM_BASE;
97
98 *(unsigned long *)CPU_RELEASE_ADDR = 0;
99
100 puts("DRAM size:");
101
102 return 0;
103 }
104
105 /*
106 * Board specific reset that is system reset.
107 */
reset_cpu(void)108 void reset_cpu(void)
109 {
110 }
111
112 /*
113 * Board specific ethernet initialization routine.
114 */
board_eth_init(struct bd_info * bis)115 int board_eth_init(struct bd_info *bis)
116 {
117 int rc = 0;
118
119 return rc;
120 }
121