1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2010-2020 CS Group
4 * Charles Frey <charles.frey@c-s.fr>
5 * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
6 * Christophe Leroy <christophe.leroy@c-s.fr>
7 *
8 * Board specific routines for the CMPC885 board
9 */
10
11 #include <env.h>
12 #include <mpc8xx.h>
13 #include <asm/cpm_8xx.h>
14 #include <asm/io.h>
15 #include <dm.h>
16 #include <stdio.h>
17 #include <stdarg.h>
18 #include <watchdog.h>
19 #include <serial.h>
20 #include <hang.h>
21 #include <flash.h>
22 #include <init.h>
23 #include <fdt_support.h>
24 #include <linux/delay.h>
25 #include <spi.h>
26
27 #include "../common/common.h"
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 #define ADDR_CPLD_R_RESET ((unsigned short __iomem *)CONFIG_CPLD_BASE)
32 #define ADDR_CPLD_R_ETAT ((unsigned short __iomem *)(CONFIG_CPLD_BASE + 2))
33 #define ADDR_CPLD_R_TYPE ((unsigned char __iomem *)(CONFIG_CPLD_BASE + 3))
34
35 #define PATH_PHY2 "/soc@ff000000/mdio@e00/ethernet-phy@2"
36 #define PATH_PHY3 "/soc@ff000000/mdio@e00/ethernet-phy@3"
37 #define PATH_ETH1 "/soc@ff000000/ethernet@1e00"
38 #define FIBER_PHY PATH_PHY2
39
40 #define R_ETAT_PRES_BASE 0x0040
41
42 #define R_RESET_STATUS 0x0400
43 #define R_RST_STATUS 0x0004
44
ft_board_setup(void * blob,struct bd_info * bd)45 int ft_board_setup(void *blob, struct bd_info *bd)
46 {
47 const char *sync = "receive";
48
49 ft_cpu_setup(blob, bd);
50
51 /* BRG */
52 do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency", bd->bi_busfreq, 1);
53
54 /* MAC addr */
55 fdt_fixup_ethernet(blob);
56
57 /* Bus Frequency for CPM */
58 do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
59
60 /* E1 interface - Set data rate */
61 do_fixup_by_path_u32(blob, "/localbus/e1", "data-rate", 2, 1);
62
63 /* E1 interface - Set channel phase to 0 */
64 do_fixup_by_path_u32(blob, "/localbus/e1", "channel-phase", 0, 1);
65
66 /* E1 interface - rising edge sync pulse transmit */
67 do_fixup_by_path(blob, "/localbus/e1", "rising-edge-sync-pulse", sync, strlen(sync), 1);
68
69 /* MIAE only */
70 if (!(in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE))
71 return 0;
72
73 return ft_board_setup_common(blob);
74 }
75
ft_board_setup_phy3(void)76 void ft_board_setup_phy3(void)
77 {
78 /* switch to phy3 with gpio, we'll only use phy3 */
79 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
80 cpm8xx_t __iomem *cp = (cpm8xx_t __iomem *)&immr->im_cpm;
81
82 setbits_be32(&cp->cp_pedat, 0x00002000);
83 }
84
checkboard(void)85 int checkboard(void)
86 {
87 serial_puts("Board: ");
88
89 /* Is a motherboard present ? */
90 if (in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE)
91 return checkboard_common();
92
93 printf("CMPC885 (CS GROUP)\n");
94
95 return 0;
96 }
97
98 #define MAX_SPI_BYTES 0x20
99
100 #define EE_OFF_MAC1 0x10
101 #define EE_OFF_MAC2 0x16
102
103 /* Reads MAC addresses from SPI EEPROM */
setup_mac(void)104 static int setup_mac(void)
105 {
106 uchar din[MAX_SPI_BYTES];
107 int ret;
108 unsigned long ident = 0x08005120;
109
110 ret = read_eeprom(din, sizeof(din));
111 if (ret)
112 return ret;
113
114 if (memcmp(din + EE_OFF_MAC1, &ident, sizeof(ident)) == 0)
115 eth_env_set_enetaddr("ethaddr", din + EE_OFF_MAC1);
116
117 if (memcmp(din + EE_OFF_MAC2, &ident, sizeof(ident)) == 0) {
118 eth_env_set_enetaddr("eth1addr", din + EE_OFF_MAC2);
119 eth_env_set_enetaddr("eth2addr", din + EE_OFF_MAC2);
120 }
121
122 return 0;
123 }
124
misc_init_r(void)125 int misc_init_r(void)
126 {
127 /* Verify mother board presence */
128 if (in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE) {
129 misc_init_r_common();
130 } else {
131 env_set("config", CFG_BOARD_CMPCXXX);
132 env_set("hostname", CFG_BOARD_CMPCXXX);
133 }
134
135 if (setup_mac())
136 printf("Error retrieving mac addresses\n");
137
138 /* Protection ON by default */
139 flash_protect(FLAG_PROTECT_SET, CFG_SYS_FLASH_BASE, 0xffffffff, &flash_info[0]);
140
141 return 0;
142 }
143
iop_setup_mcr(void)144 void iop_setup_mcr(void)
145 {
146 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
147 iop8xx_t __iomem *iop = &immr->im_ioport;
148 cpm8xx_t __iomem *cp = &immr->im_cpm;
149
150 /* Wait reset on FPGA_F */
151 udelay(100);
152
153 /* We must initialize data before changing direction */
154 setbits_be16(&iop->iop_pcdat, 0x088E);
155 setbits_be16(&iop->iop_pddat, 0x0001);
156 setbits_be32(&cp->cp_pbdat, 0x00029510);
157 setbits_be32(&cp->cp_pedat, 0x00000002);
158
159 /*
160 * PAPAR[13] = 0 [0x0004] -> GPIO: ()
161 * PAPAR[12] = 0 [0x0008] -> GPIO: ()
162 * PAPAR[9] = 1 [0x0040] -> GPIO: (PCM_IN_12_MPC)
163 * PAPAR[8] = 1 [0x0080] -> GPIO: (PCM_OUT_12_MPC)
164 * PAPAR[7] = 1 [0x0100] -> GPIO: (TDM_BCLK_MPC)
165 * PAPAR[6] = 1 [0x0200] -> GPIO: (CLK2)
166 */
167 clrsetbits_be16(&iop->iop_papar, 0x03CC, 0x03C0);
168
169 /*
170 * PBODR[16] = 1 [0x00008000] -> GPIO: (PROG_FPGA_MEZZ)
171 */
172 setbits_be16(&cp->cp_pbodr, 0x00008000);
173
174 /*
175 * PBDIR[27] = 1 [0x00000010] -> GPIO: (WR_TEMP2)
176 * PBDIR[26] = 1 [0x00000020] -> GPIO: (BRG02)
177 * PBDIR[23] = 1 [0x00000100] -> GPIO: (CS_TEMP2)
178 * PBDIR[18] = 1 [0x00002000] -> GPIO: (RTS2)
179 * PBDIR[16] = 1 [0x00008000] -> GPIO: (PROG_FPGA_MEZZ)
180 * PBDIR[15] = 1 [0x00010000] -> GPIO: (BRG03)
181 * PBDIR[14] = 1 [0x00020000] -> GPIO: (CS_TEMP)
182 */
183 setbits_be32(&cp->cp_pbdir, 0x0003A130);
184
185 /*
186 * PBPAR[20] = 1 [0x00000800] -> GPIO: (SMRXD2)
187 * PBPAR[17] = 0 [0x00004000] -> GPIO: (DONE_FPGA_MEZZ)
188 * PBPAR[16] = 0 [0x00008000] -> GPIO: (PROG_FPGA_MEZZ)
189 */
190 clrsetbits_be32(&cp->cp_pbpar, 0x0000C800, 0x00000800);
191
192 /*
193 * PCPAR[14] = 0 [0x0002] -> GPIO: (CS_POT2)
194 */
195 clrbits_be16(&iop->iop_pcpar, 0x0002);
196
197 /*
198 * PDPAR[14] = 1 [0x0002] -> GPIO: (TDM_FS_MPC)
199 * PDPAR[11] = 1 [0x0010] -> GPIO: (RXD3)
200 * PDPAR[10] = 1 [0x0020] -> GPIO: (TXD3)
201 * PDPAR[9] = 1 [0x0040] -> GPIO: (TXD4)
202 * PDPAR[7] = 1 [0x0100] -> GPIO: (RTS3)
203 * PDPAR[5] = 1 [0x0400] -> GPIO: (CLK8)
204 * PDPAR[3] = 1 [0x1000] -> GPIO: (CLK7)
205 */
206 setbits_be16(&iop->iop_pdpar, 0x1572);
207
208 /*
209 * PEPAR[27] = 1 [0x00000010] -> GPIO: (R2_RXER)
210 * PEPAR[26] = 1 [0x00000020] -> GPIO: (R2_CRS_DV)
211 * PEPAR[25] = 1 [0x00000040] -> GPIO: (RXD4)
212 * PEPAR[24] = 1 [0x00000080] -> GPIO: (BRG01)
213 * PEPAR[23] = 0 [0x00000100] -> GPIO: (DONE_FPGA_RADIO)
214 * PEPAR[22] = 1 [0x00000200] -> GPIO: (R2_RXD1)
215 * PEPAR[21] = 1 [0x00000400] -> GPIO: (R2_RXD0)
216 * PEPAR[20] = 1 [0x00000800] -> GPIO: (SMTXD2)
217 * PEPAR[19] = 1 [0x00001000] -> GPIO: (R2_TXEN)
218 * PEPAR[17] = 1 [0x00004000] -> GPIO: (CLK5)
219 * PEPAR[16] = 1 [0x00008000] -> GPIO: (R2_REF_CLK)
220 * PEPAR[15] = 1 [0x00010000] -> GPIO: (R2_TXD1)
221 * PEPAR[14] = 1 [0x00020000] -> GPIO: (R2_TXD0)
222 */
223 clrsetbits_be32(&cp->cp_pepar, 0x0003DFF0, 0x0003DEF0);
224
225 /*
226 * PADIR[9] = 1 [0x0040] -> GPIO: (PCM_IN_12_MPC)
227 * PADIR[8] = 1 [0x0080] -> GPIO: (PCM_OUT_12_MPC)
228 * PADIR[5] = 1 [0x0400] -> GPIO: ()
229 */
230 setbits_be16(&iop->iop_padir, 0x04C0);
231
232 /*
233 * PCDIR[15] = 1 [0x0001] -> GPIO: (WP_EEPROM2)
234 * PCDIR[14] = 1 [0x0002] -> GPIO: (CS_POT2)
235 * PCDIR[13] = 1 [0x0004] -> GPIO: (CS_POT1)
236 * PCDIR[12] = 1 [0x0008] -> GPIO: (CS_EEPROM2)
237 * PCDIR[8] = 1 [0x0080] -> GPIO: (CS_CODEC_FAV)
238 * PCDIR[4] = 1 [0x0800] -> GPIO: (CS_CODEC_RADIO)
239 */
240 setbits_be16(&iop->iop_pcdir, 0x088F);
241
242 /*
243 * PDDIR[9] = 1 [0x0040] -> GPIO: (TXD4)
244 * PDDIR[6] = 0 [0x0200] -> GPIO: (INIT_FPGA_RADIO)
245 * PDDIR[2] = x [0x2000] -> Reserved
246 * PDDIR[1] = 0 [0x4000] -> ODR for PD10 : (TXD3)
247 * PDDIR[0] = 0 [0x8000] -> ODR for PD8 : (R_MDC)
248 */
249 clrsetbits_be16(&iop->iop_pddir, 0xC240, 0x0040);
250
251 /*
252 * PEDIR[30] = 1 [0x00000002] -> GPIO: (FPGA_FIRMWARE)
253 * PEDIR[27] = 1 [0x00000010] -> GPIO: (R2_RXER)
254 * PEDIR[26] = 1 [0x00000020] -> GPIO: (R2_CRS_DV)
255 * PEDIR[23] = 0 [0x00000100] -> GPIO: (DONE_FPGA_RADIO)
256 * PEDIR[22] = 1 [0x00000200] -> GPIO: (R2_RXD1)
257 * PEDIR[21] = 1 [0x00000400] -> GPIO: (R2_RXD0)
258 * PEDIR[19] = 1 [0x00001000] -> GPIO: (R2_TXEN)
259 * PEDIR[18] = 1 [0x00002000] -> GPIO: (PROG_FPGA_RADIO)
260 * PEDIR[16] = 1 [0x00008000] -> GPIO: (R2_REF_CLK)
261 * PEDIR[15] = 1 [0x00010000] -> GPIO: (R2_TXD1)
262 * PEDIR[14] = 1 [0x00020000] -> GPIO: (R2_TXD0)
263 */
264 clrsetbits_be32(&cp->cp_pedir, 0x0003B732, 0x0003B632);
265
266 /*
267 * PAODR[10] = 1 [0x0020] -> GPIO: (INIT_FPGA_F)
268 */
269 setbits_be16(&iop->iop_paodr, 0x0020); // set_bit
270
271 /*
272 * PEODR[30] = 1 [0x00000002] -> GPIO: (FPGA_FIRMWARE)
273 * PEODR[18] = 1 [0x00002000] -> GPIO: (FPGA_RADIO)
274 */
275 setbits_be32(&cp->cp_peodr, 0x00002002);
276
277 /*
278 * PESO[24] = 1 [0x00000080] -> GPIO: (BRG01)
279 * PESO[23] = 0 [0x00000100] -> GPIO: (DONE_FPGA_RADIO)
280 * PESO[20] = 1 [0x00000800] -> GPIO: (SMTXD2)
281 * PESO[19] = 1 [0x00001000] -> GPIO: (R2_TXEN)
282 * PESO[15] = 1 [0x00010000] -> GPIO: (R2_TXD1)
283 * PESO[14] = 1 [0x00020000] -> GPIO: (R2_TXD0)
284 */
285 clrsetbits_be32(&cp->cp_peso, 0x00031980, 0x00031880);
286
287 /* Disable CS for device */
288 /* PROGFPGA down */
289 clrbits_be32(&cp->cp_pbdat, 0x00008000);
290
291 /* PROGFPGA down */
292 clrbits_be32(&cp->cp_pedat, 0x00002000);
293 udelay(1); /* Wait more than 300ns */
294
295 /*
296 * We do not set the PROG signal of the C4E1 because
297 * there is a conflic with the CS of the EEPROM.
298 * I don't know why there is not the same problem
299 * with the FPGA_R
300 */
301
302 /* PROGFPGA up */
303 setbits_be32(&cp->cp_pedat, 0x00002000);
304 }
305
iop_setup_cmpc885(void)306 static void iop_setup_cmpc885(void)
307 {
308 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
309 iop8xx_t __iomem *iop = &immr->im_ioport;
310 cpm8xx_t __iomem *cp = &immr->im_cpm;
311
312 /* We must initialize data before changing direction */
313 out_be16(&iop->iop_pcdat, 0x0000);
314 out_be16(&iop->iop_pddat, 0x0001);
315
316 out_be32(&cp->cp_pbdat, 0x00021400);
317 out_be32(&cp->cp_pedat, 0x00000000);
318
319 /*
320 * PAPAR[13] = 0 [0x0004] -> GPIO: ()
321 * PAPAR[12] = 0 [0x0008] -> GPIO: ()
322 * PAPAR[9] = 0 [0x0040] -> GPIO: ()
323 * PAPAR[8] = 0 [0x0080] -> GPIO: ()
324 * PAPAR[7] = 0 [0x0100] -> GPIO: ()
325 * PAPAR[6] = 0 [0x0200] -> GPIO: ()
326 */
327 clrbits_be16(&iop->iop_papar, 0x03CC);
328
329 /*
330 * PBPAR[20] = 0 [0x00000800] -> GPIO: ()
331 * PBPAR[17] = 0 [0x00004000] -> GPIO: ()
332 * PBPAR[16] = 0 [0x00008000] -> GPIO: ()
333 */
334 clrbits_be32(&cp->cp_pbpar, 0x0000C800);
335
336 /*
337 * PCPAR[14] = 0 [0x0002] -> GPIO: ()
338 */
339 clrbits_be16(&iop->iop_pcpar, 0x0002);
340
341 /*
342 * PDPAR[14] = 0 [0x0002] -> GPIO: ()
343 * PDPAR[11] = 0 [0x0010] -> GPIO: ()
344 * PDPAR[10] = 0 [0x0020] -> GPIO: ()
345 * PDPAR[9] = 0 [0x0040] -> GPIO: ()
346 * PDPAR[7] = 0 [0x0100] -> GPIO: ()
347 * PDPAR[5] = 0 [0x0400] -> GPIO: ()
348 * PDPAR[3] = 0 [0x1000] -> GPIO: ()
349 */
350 clrbits_be16(&iop->iop_pdpar, 0x1572);
351
352 /*
353 * PEPAR[27] = 0 [0x00000010] -> GPIO: ()
354 * PEPAR[26] = 0 [0x00000020] -> GPIO: ()
355 * PEPAR[25] = 0 [0x00000040] -> GPIO: ()
356 * PEPAR[24] = 0 [0x00000080] -> GPIO: ()
357 * PEPAR[23] = 0 [0x00000100] -> GPIO: ()
358 * PEPAR[22] = 0 [0x00000200] -> GPIO: ()
359 * PEPAR[21] = 0 [0x00000400] -> GPIO: ()
360 * PEPAR[20] = 0 [0x00000800] -> GPIO: ()
361 * PEPAR[19] = 0 [0x00001000] -> GPIO: ()
362 * PEPAR[17] = 0 [0x00004000] -> GPIO: ()
363 * PEPAR[16] = 0 [0x00008000] -> GPIO: ()
364 * PEPAR[15] = 0 [0x00010000] -> GPIO: ()
365 * PEPAR[14] = 0 [0x00020000] -> GPIO: ()
366 */
367 clrbits_be32(&cp->cp_pepar, 0x0003DFF0);
368
369 /*
370 * PADIR[9] = 0 [0x0040] -> GPIO: ()
371 * PADIR[8] = 0 [0x0080] -> GPIO: ()
372 * PADIR[5] = 0 [0x0400] -> GPIO: ()
373 */
374 clrbits_be16(&iop->iop_padir, 0x04C0);
375
376 /*
377 * In/Out or per. Function 0/1
378 * PBDIR[27] = 0 [0x00000010] -> GPIO: ()
379 * PBDIR[26] = 0 [0x00000020] -> GPIO: ()
380 * PBDIR[23] = 0 [0x00000100] -> GPIO: ()
381 * PBDIR[17] = 0 [0x00004000] -> GPIO: ()
382 * PBDIR[16] = 0 [0x00008000] -> GPIO: ()
383 */
384 clrbits_be32(&cp->cp_pbdir, 0x0000C130);
385
386 /*
387 * PCDIR[15] = 0 [0x0001] -> GPIO: ()
388 * PCDIR[14] = 0 [0x0002] -> GPIO: ()
389 * PCDIR[13] = 0 [0x0004] -> GPIO: ()
390 * PCDIR[12] = 0 [0x0008] -> GPIO: ()
391 * PCDIR[8] = 0 [0x0080] -> GPIO: ()
392 * PCDIR[4] = 0 [0x0800] -> GPIO: ()
393 */
394 clrbits_be16(&iop->iop_pcdir, 0x088F);
395
396 /*
397 * PDDIR[9] = 0 [0x0040] -> GPIO: ()
398 * PDDIR[6] = 0 [0x0200] -> GPIO: ()
399 * PDDIR[2] = x [0x2000] -> Reserved
400 * PDDIR[1] = 0 [0x4000] -> ODR for PD10 : ()
401 * PDDIR[0] = 0 [0x8000] -> ODR for PD8 : (R_MDC)
402 */
403 clrbits_be16(&iop->iop_pddir, 0xC240);
404
405 /*
406 * PEDIR[30] = 0 [0x00000002] -> GPIO: ()
407 * PEDIR[27] = 0 [0x00000010] -> GPIO: ()
408 * PEDIR[26] = 0 [0x00000020] -> GPIO: ()
409 * PEDIR[23] = 0 [0x00000100] -> GPIO: ()
410 * PEDIR[22] = 0 [0x00000200] -> GPIO: ()
411 * PEDIR[21] = 0 [0x00000400] -> GPIO: ()
412 * PEDIR[19] = 0 [0x00001000] -> GPIO: ()
413 * PEDIR[18] = 0 [0x00002000] -> GPIO: ()
414 * PEDIR[16] = 0 [0x00008000] -> GPIO: ()
415 * PEDIR[15] = 0 [0x00010000] -> GPIO: ()
416 * PEDIR[14] = 0 [0x00020000] -> GPIO: ()
417 */
418 clrbits_be32(&cp->cp_pedir, 0x0003B732);
419
420 /*
421 * PAODR[10] = 0 [0x0020] -> GPIO: ()
422 */
423 clrbits_be16(&iop->iop_paodr, 0x0020);
424
425 /*
426 * PBODR[16] = 0 [0x00008000] -> GPIO: ()
427 */
428 clrbits_be16(&cp->cp_pbodr, 0x00008000);
429
430 /*
431 * PEODR[30] = 0 [0x00000002] -> GPIO: ()
432 * PEODR[18] = 0 [0x00002000] -> GPIO: ()
433 */
434 clrbits_be32(&cp->cp_peodr, 0x00002002);
435
436 /*
437 * PESO[24] = 0 [0x00000080] -> GPIO: ()
438 * PESO[23] = 0 [0x00000100] -> GPIO: ()
439 * PESO[20] = 0 [0x00000800] -> GPIO: ()
440 * PESO[19] = 0 [0x00001000] -> GPIO: ()
441 * PESO[15] = 0 [0x00010000] -> GPIO: ()
442 * PESO[14] = 0 [0x00020000] -> GPIO: ()
443 */
444 clrbits_be32(&cp->cp_peso, 0x00031980);
445 }
446
iop_setup_miae(void)447 void iop_setup_miae(void)
448 {
449 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
450 iop8xx_t __iomem *iop = &immr->im_ioport;
451 cpm8xx_t __iomem *cp = &immr->im_cpm;
452
453 /* Wait reset on FPGA_F */
454 udelay(100);
455
456 /* Load CPM relocation code */
457 cpm_load_patch(cp);
458
459 /* Set the front panel LED color to red */
460 clrbits_8((unsigned char __iomem *)CONFIG_FPGA_BASE + 0x44, 0x02);
461
462 /* We must initialize data before changing direction */
463 setbits_be16(&iop->iop_pcdat, 0x0888);
464 setbits_be16(&iop->iop_pddat, 0x0201);
465 setbits_be32(&cp->cp_pbdat, 0x00021510);
466 setbits_be32(&cp->cp_pedat, 0x00000002);
467
468 /*
469 * PAPAR[13] = 1 [0x0004] -> GPIO: (RXD2)
470 * PAPAR[12] = 1 [0x0008] -> GPIO: (TXD2)
471 * PAPAR[9] = 1 [0x0040] -> GPIO: (TDM1O)
472 * PAPAR[8] = 1 [0x0080] -> GPIO: (TDM1I)
473 * PAPAR[7] = 1 [0x0100] -> GPIO: (TDM_BCLK_MPC)
474 * PAPAR[6] = 1 [0x0200] -> GPIO: (CLK2)
475 */
476 setbits_be16(&iop->iop_papar, 0x03CC);
477
478 /*
479 * PBODR[16] = 0 [0x00008000] -> GPIO: (L1ST4)
480 */
481 clrbits_be16(&cp->cp_pbodr, 0x00008000);
482
483 /*
484 * PBDIR[27] = 1 [0x00000010] -> GPIO: (WR_TEMP2)
485 * PBDIR[26] = 1 [0x00000020] -> GPIO: (BRG02)
486 * PBDIR[23] = 1 [0x00000100] -> GPIO: (CS_TEMP2)
487 * PBDIR[18] = 1 [0x00002000] -> GPIO: (RTS2)
488 * PBDIR[16] = 0 [0x00008000] -> GPIO: (L1ST4)
489 * PBDIR[15] = 1 [0x00010000] -> GPIO: (BRG03)
490 * PBDIR[14] = 1 [0x00020000] -> GPIO: (CS_TEMP)
491 */
492 clrsetbits_be32(&cp->cp_pbdir, 0x0003A130, 0x00032130);
493
494 /*
495 * PBPAR[20] = 1 [0x00000800] -> GPIO: (SMRXD2)
496 * PBPAR[17] = 1 [0x00004000] -> GPIO: (L1ST3)
497 * PBPAR[16] = 1 [0x00008000] -> GPIO: (L1ST4)
498 */
499 setbits_be32(&cp->cp_pbpar, 0x0000C800);
500
501 /*
502 * PCPAR[14] = 1 [0x0002] -> GPIO: (L1ST2)
503 */
504 setbits_be16(&iop->iop_pcpar, 0x0002);
505
506 /*
507 * PDPAR[14] = 1 [0x0002] -> GPIO: (TDM_FS_MPC)
508 * PDPAR[11] = 1 [0x0010] -> GPIO: (RXD3)
509 * PDPAR[10] = 1 [0x0020] -> GPIO: (TXD3)
510 * PDPAR[9] = 1 [0x0040] -> GPIO: (TXD4)
511 * PDPAR[7] = 1 [0x0100] -> GPIO: (RTS3)
512 * PDPAR[5] = 1 [0x0400] -> GPIO: (CLK8)
513 * PDPAR[3] = 1 [0x1000] -> GPIO: (CLK7)
514 */
515 setbits_be16(&iop->iop_pdpar, 0x1572);
516
517 /*
518 * PEPAR[27] = 1 [0x00000010] -> GPIO: (R2_RXER)
519 * PEPAR[26] = 1 [0x00000020] -> GPIO: (R2_CRS_DV)
520 * PEPAR[25] = 1 [0x00000040] -> GPIO: (RXD4)
521 * PEPAR[24] = 1 [0x00000080] -> GPIO: (BRG01)
522 * PEPAR[23] = 1 [0x00000100] -> GPIO: (L1ST1)
523 * PEPAR[22] = 1 [0x00000200] -> GPIO: (R2_RXD1)
524 * PEPAR[21] = 1 [0x00000400] -> GPIO: (R2_RXD0)
525 * PEPAR[20] = 1 [0x00000800] -> GPIO: (SMTXD2)
526 * PEPAR[19] = 1 [0x00001000] -> GPIO: (R2_TXEN)
527 * PEPAR[17] = 1 [0x00004000] -> GPIO: (CLK5)
528 * PEPAR[16] = 1 [0x00008000] -> GPIO: (R2_REF_CLK)
529 * PEPAR[15] = 1 [0x00010000] -> GPIO: (R2_TXD1)
530 * PEPAR[14] = 1 [0x00020000] -> GPIO: (R2_TXD0)
531 */
532 setbits_be32(&cp->cp_pepar, 0x0003DFF0);
533
534 /*
535 * PADIR[9] = 1 [0x0040] -> GPIO: (TDM1O)
536 * PADIR[8] = 1 [0x0080] -> GPIO: (TDM1I)
537 * PADIR[5] = 0 [0x0400] -> GPIO: ()
538 */
539 clrsetbits_be16(&iop->iop_padir, 0x04C0, 0x00C0);
540
541 /*
542 * PCDIR[15] = 1 [0x0001] -> GPIO: (WP_EEPROM2)
543 * PCDIR[14] = 1 [0x0002] -> GPIO: (L1ST2)
544 * PCDIR[13] = 0 [0x0004] -> GPIO: ()
545 * PCDIR[12] = 1 [0x0008] -> GPIO: (CS_EEPROM2)
546 * PCDIR[8] = 1 [0x0080] -> GPIO: (CS_CODEC_2)
547 * PCDIR[4] = 1 [0x0800] -> GPIO: (CS_CODEC_1)
548 */
549 clrsetbits_be16(&iop->iop_pcdir, 0x088F, 0x088B);
550
551 /*
552 * PDDIR[9] = 1 [0x0040] -> GPIO: (TXD4)
553 * PDDIR[6] = 1 [0x0200] -> GPIO: (CS_CODEC_3)
554 */
555 setbits_be16(&iop->iop_pddir, 0x0240);
556
557 /*
558 * PEDIR[30] = 1 [0x00000002] -> GPIO: (FPGA_FIRMWARE)
559 * PEDIR[27] = 1 [0x00000010] -> GPIO: (R2_RXER)
560 * PEDIR[26] = 1 [0x00000020] -> GPIO: (R2_CRS_DV)
561 * PEDIR[23] = 1 [0x00000100] -> GPIO: (L1ST1)
562 * PEDIR[22] = 1 [0x00000200] -> GPIO: (R2_RXD1)
563 * PEDIR[21] = 1 [0x00000400] -> GPIO: (R2_RXD0)
564 * PEDIR[19] = 1 [0x00001000] -> GPIO: (R2_TXEN)
565 * PEDIR[18] = 1 [0x00002000] -> GPIO: (PE18)
566 * PEDIR[16] = 1 [0x00008000] -> GPIO: (R2_REF_CLK)
567 * PEDIR[15] = 1 [0x00010000] -> GPIO: (R2_TXD1)
568 * PEDIR[14] = 1 [0x00020000] -> GPIO: (R2_TXD0)
569 */
570 setbits_be32(&cp->cp_pedir, 0x0003B732);
571
572 /*
573 * PAODR[10] = 1 [0x0020] -> GPIO: (INIT_FPGA_F)
574 */
575 setbits_be16(&iop->iop_paodr, 0x0020);
576
577 /*
578 * PEODR[30] = 1 [0x00000002] -> GPIO: (FPGA_FIRMWARE)
579 * PEODR[18] = 0 [0x00002000] -> GPIO: (PE18)
580 */
581 clrsetbits_be32(&cp->cp_peodr, 0x00002002, 0x00000002);
582
583 /*
584 * PESO[24] = 1 [0x00000080] -> GPIO: (BRG01)
585 * PESO[23] = 1 [0x00000100] -> GPIO: (L1ST1)
586 * PESO[20] = 1 [0x00000800] -> GPIO: (SMTXD2)
587 * PESO[19] = 1 [0x00001000] -> GPIO: (R2_TXEN)
588 * PESO[15] = 1 [0x00010000] -> GPIO: (R2_TXD1)
589 * PESO[14] = 1 [0x00020000] -> GPIO: (R2_TXD0)
590 */
591 setbits_be32(&cp->cp_peso, 0x00031980);
592 }
593
594 /* Specific board initialization */
board_early_init_f(void)595 int board_early_init_f(void)
596 {
597 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
598 iop8xx_t __iomem *iop = &immr->im_ioport;
599 cpm8xx_t __iomem *cp = &immr->im_cpm;
600
601 /* MPC885 Port settings common to all boards */
602 setbits_be16(&iop->iop_padat, 0x0000);
603
604 /* Port A (MPC885 reference manual - 34.2) */
605 /*
606 * In/Out or per. Function 0/1
607 * PADIR[15] = 0 [0x0001] -> GPIO: (USB_RXD)
608 * PADIR[14] = 0 [0x0002] -> GPIO: (USB_OE)
609 * PADIR[13] = 0 [0x0004] -> GPIO: ()
610 * PADIR[12] = 0 [0x0008] -> GPIO: ()
611 * PADIR[11] = 1 [0x0010] -> GPIO: (R1_TXD0)
612 * PADIR[10] = 0 [0x0020] -> GPIO: ()
613 * PADIR[7] = 0 [0x0100] -> GPIO: ()
614 * PADIR[6] = 0 [0x0200] -> GPIO: ()
615 * PADIR[4] = 1 [0x0800] -> GPIO: (R1_TXD1)
616 * PADIR[3] = 0 [0x1000] -> GPIO: (R1_RXER)
617 * PADIR[2] = 0 [0x2000] -> GPIO: (R1_CRS_DV)
618 * PADIR[1] = 0 [0x4000] -> GPIO: (R1_RXD0)
619 * PADIR[0] = 0 [0x8000] -> GPIO: (R1_RXD1)
620 */
621 clrsetbits_be16(&iop->iop_padir, 0xFB3F, 0x0810);
622
623 /*
624 * Open drain or active output
625 * PAODR[15] = x [0x0001]
626 * PAODR[14] = 0 [0x0002]
627 * PAODR[13] = x [0x0004]
628 * PAODR[12] = 0 [0x0008]
629 * PAODR[11] = 0 [0x0010]
630 * PAODR[9] = 0 [0x0040]
631 * PAODR[8] = 0 [0x0080]
632 * PAODR[7] = 0 [0x0100]
633 */
634 clrbits_be16(&iop->iop_paodr, 0x01DF);
635
636 /*
637 * GPIO or per. Function
638 * PAPAR[15] = 1 [0x0001] -> GPIO: (USB_RXD)
639 * PAPAR[14] = 1 [0x0002] -> GPIO: (USB_OE)
640 * PAPAR[11] = 1 [0x0010] -> GPIO: (R1_TXD0)
641 * PAPAR[10] = 0 [0x0020] -> GPIO: (INIT_FPGA_F)
642 * PAPAR[5] = 0 [0x0400] -> GPIO: ()
643 * PAPAR[4] = 1 [0x0800] -> GPIO: (R1_TXD1)
644 * PAPAR[3] = 1 [0x1000] -> GPIO: (R1_RXER)
645 * PAPAR[2] = 1 [0x2000] -> GPIO: (R1_CRS_DV)
646 * PAPAR[1] = 1 [0x4000] -> GPIO: (R1_RXD0)
647 * PAPAR[0] = 1 [0x8000] -> GPIO: (R1_RXD1)
648 */
649 clrsetbits_be16(&iop->iop_papar, 0xFC33, 0xF813);
650
651 /* Port B (MPC885 reference manual - 34.3) */
652 /*
653 * In/Out or per. Function 0/1
654 * PBDIR[31] = 0 [0x00000001] -> GPIO: (R1_REF_CLK)
655 * PBDIR[30] = 1 [0x00000002] -> GPIO: (CLK)
656 * PBDIR[29] = 1 [0x00000004] -> GPIO: (MOSI)
657 * PBDIR[28] = 1 [0x00000008] -> GPIO: (MISO)
658 * PBDIR[25] = 0 [0x00000040] -> GPIO: (SMTXD1)
659 * PBDIR[24] = 0 [0x00000080] -> GPIO: (SMRXD1)
660 * PBDIR[22] = 0 [0x00000200] -> GPIO: (INIT_FPGA_MEZZ)
661 * PBDIR[21] = 1 [0x00000400] -> GPIO: (CS_EEPROM)
662 * PBDIR[20] = 0 [0x00000800] -> GPIO: (SMRXD2)
663 * PBDIR[19] = 1 [0x00001000] -> GPIO: (WR_TEMP)
664 * PBDIR[17] = 0 [0x00004000] -> GPIO: (DONE_FPGA_MEZZ)
665 */
666 clrsetbits_be32(&cp->cp_pbdir, 0x00005ECF, 0x0000140E);
667
668 /*
669 * Open drain or active output
670 * PBODR[31] = 0 [0x00000001] -> GPIO: (R1_REF_CLK)
671 * PBODR[30] = 0 [0x00000002] -> GPIO: (CLK)
672 * PBODR[29] = 0 [0x00000004] -> GPIO: (MOSI)
673 * PBODR[28] = 0 [0x00000008] -> GPIO: (MISO)
674 * PBODR[27] = 0 [0x00000010] -> GPIO: (WR_TEMP2)
675 * PBODR[26] = 0 [0x00000020] -> GPIO: (BRG02)
676 * PBODR[25] = 0 [0x00000040] -> GPIO: (SMTXD1)
677 * PBODR[24] = 0 [0x00000080] -> GPIO: (SMRXD1)
678 * PBODR[23] = 0 [0x00000100] -> GPIO: (CS_TEMP2)
679 * PBODR[22] = 0 [0x00000200] -> GPIO: (INIT_FPGA_MEZZ)
680 * PBODR[21] = 0 [0x00000400] -> GPIO: (CS_EEPROM)
681 * PBODR[20] = 0 [0x00000800] -> GPIO: (SMRXD2)
682 * PBODR[19] = 0 [0x00001000] -> GPIO: (WR_TEMP)
683 * PBODR[18] = 0 [0x00002000] -> GPIO: (RTS2)
684 * PBODR[17] = 0 [0x00004000] -> GPIO: (DONE_FPGA_MEZZ)
685 */
686 clrbits_be16(&cp->cp_pbodr, 0x00007FFF);
687
688 /*
689 * GPIO or per. Function
690 * PBPAR[31] = 1 [0x00000001] -> GPIO: (R1_REF_CLK)
691 * PBPAR[30] = 1 [0x00000002] -> GPIO: (CLK)
692 * PBPAR[29] = 1 [0x00000004] -> GPIO: (MOSI)
693 * PBPAR[28] = 1 [0x00000008] -> GPIO: (MISO)
694 * PBPAR[27] = 0 [0x00000010] -> GPIO: (WR_TEMP2)
695 * PBPAR[26] = 0 [0x00000020] -> GPIO: (BRG02)
696 * PBPAR[25] = 1 [0x00000040] -> GPIO: (SMTXD1)
697 * PBPAR[24] = 1 [0x00000080] -> GPIO: (SMRXD1)
698 * PBPAR[23] = 0 [0x00000100] -> GPIO: (CS_TEMP2)
699 * PBPAR[22] = 0 [0x00000200] -> GPIO: (INIT_FPGA_MEZZ)
700 * PBPAR[21] = 0 [0x00000400] -> GPIO: (CS_EEPROM)
701 * PBPAR[19] = 0 [0x00001000] -> GPIO: (WR_TEMP)
702 * PBPAR[18] = 0 [0x00002000] -> GPIO: (RTS2)
703 * PBPAR[15] = 0 [0x00010000] -> GPIO: (BRG03)
704 * PBPAR[14] = 0 [0x00020000] -> GPIO: (CS_TEMP)
705 */
706 clrsetbits_be32(&cp->cp_pbpar, 0x000337FF, 0x000000CF);
707
708 /* Port C (MPC885 Reference Manual - 34.4) */
709 /*
710 * In/Out or per. Function 0/1
711 * PCDIR[11] = 0 [0x0010] -> GPIO: (USB_RXP)
712 * PCDIR[10] = 0 [0x0020] -> GPIO: (USB_RXN)
713 * PCDIR[9] = 0 [0x0040] -> GPIO: (CTS2)
714 * PCDIR[7] = 1 [0x0100] -> GPIO: (USB_TXP)
715 * PCDIR[6] = 1 [0x0200] -> GPIO: (USB_TXN)
716 * PCDIR[5] = 0 [0x0400] -> GPIO: (CTS3)
717 */
718 clrsetbits_be16(&iop->iop_pcdir, 0x0770, 0x0300);
719
720 /*
721 * GPIO or per. Function
722 * PCPAR[15] = 0 [0x0001] -> GPIO: (WP_EEPROM2)
723 * PCPAR[13] = 0 [0x0004] -> GPIO: (CS_POT1)
724 * PCPAR[12] = 0 [0x0008] -> GPIO: (CS_EEPROM2)
725 * PCPAR[11] = 0 [0x0010] -> GPIO: (USB_RXP)
726 * PCPAR[10] = 0 [0x0020] -> GPIO: (USB_RXN)
727 * PCPAR[9] = 0 [0x0040] -> GPIO: (CTS2)
728 * PCPAR[8] = 0 [0x0080] -> GPIO: (CS_CODEC_FAV)
729 * PCPAR[7] = 1 [0x0100] -> GPIO: (USB_TXP)
730 * PCPAR[6] = 1 [0x0200] -> GPIO: (USB_TXN)
731 * PCPAR[5] = 0 [0x0400] -> GPIO: (CTS3)
732 * PCPAR[4] = 0 [0x0800] -> GPIO: (CS_CODEC_RADIO)
733 */
734 clrsetbits_be16(&iop->iop_pcpar, 0x0FFD, 0x0300);
735
736 /*
737 * Special Option register
738 * PCSO[15] = 0 [0x0001] -> GPIO: (WP_EEPROM2)
739 * PCSO[14] = 0 [0x0002] -> GPIO: (CS_POT2)
740 * PCSO[13] = x [0x0004] -> Reserved
741 * PCSO[12] = x [0x0008] -> Reserved
742 * PCSO[11] = 1 [0x0010] -> GPIO: (USB_RXP)
743 * PCSO[10] = 1 [0x0020] -> GPIO: (USB_RXN)
744 * PCSO[9] = 1 [0x0040] -> GPIO: (CTS2)
745 * PCSO[8] = 0 [0x0080] -> GPIO: (CS_CODEC_FAV)
746 * PCSO[7] = 0 [0x0100] -> GPIO: (USB_TXP)
747 * PCSO[6] = 0 [0x0200] -> GPIO: (USB_TXN)
748 * PCSO[5] = 1 [0x0400] -> GPIO: (CTS3)
749 * PCSO[4] = 0 [0x0800] -> GPIO: (CS_CODEC_RADIO)
750 */
751 clrsetbits_be16(&iop->iop_pcso, 0x0FF3, 0x0470);
752
753 /*
754 * Interrupt or IO
755 * PCINT[15] = 0 [0x0001] -> GPIO: ()
756 * PCINT[14] = 0 [0x0002] -> GPIO: ()
757 * PCINT[13] = 0 [0x0004] -> GPIO: ()
758 * PCINT[12] = 0 [0x0008] -> GPIO: ()
759 * PCINT[11] = 0 [0x0010] -> GPIO: (USB_RXP)
760 * PCINT[10] = 0 [0x0020] -> GPIO: (USB_RXN)
761 * PCINT[9] = 0 [0x0040] -> GPIO: ()
762 * PCINT[8] = 0 [0x0080] -> GPIO: ()
763 * PCINT[7] = 0 [0x0100] -> GPIO: (USB_TXP)
764 * PCINT[6] = 0 [0x0200] -> GPIO: (USB_TXN)
765 * PCINT[5] = 0 [0x0400] -> GPIO: ()
766 * PCINT[4] = 0 [0x0800] -> GPIO: ()
767 */
768 clrbits_be16(&iop->iop_pcint, 0x0FFF);
769
770 /* Port D (MPC885 Reference Manual - 34.5) */
771 /*
772 * In/Out or per. Function 0/1
773 * PDDIR[15] = 1 [0x0001] -> GPIO: (CS_NAND)
774 * PDDIR[14] = 0 [0x0002] -> GPIO: (TDM_FS_MPC)
775 * PDDIR[13] = 1 [0x0004] -> GPIO: (ALE_NAND)
776 * PDDIR[12] = 1 [0x0008] -> GPIO: (CLE_NAND)
777 * PDDIR[11] = 0 [0x0010] -> GPIO: (RXD3)
778 * PDDIR[10] = 0 [0x0020] -> GPIO: (TXD3)
779 * PDDIR[9] = 1 [0x0040] -> GPIO: (TXD4)
780 * PDDIR[8] = 0 [0x0080] -> GPIO: (R_MDC)
781 * PDDIR[7] = 0 [0x0100] -> GPIO: (RTS3)
782 * PDDIR[5] = 0 [0x0400] -> GPIO: (CLK8)
783 * PDDIR[4] = 0 [0x0800] -> GPIO: (CLK4)
784 * PDDIR[3] = 0 [0x1000] -> GPIO: (CLK7)
785 */
786 clrsetbits_be16(&iop->iop_pddir, 0x1DFF, 0x004D);
787
788 /*
789 * GPIO or per. Function
790 * PDPAR[15] = 0 [0x0001] -> GPIO: (CS_NAND)
791 * PDPAR[13] = 0 [0x0004] -> GPIO: (ALE_NAND)
792 * PDPAR[12] = 0 [0x0008] -> GPIO: (CLE_NAND)
793 * PDPAR[8] = 1 [0x0080] -> GPIO: (R_MDC)
794 * PDPAR[6] = 0 [0x0200] -> GPIO: (INIT_FPGA_RADIO)
795 * PDPAR[4] = 1 [0x0800] -> GPIO: (CLK4)
796 */
797 clrsetbits_be16(&iop->iop_pdpar, 0x0A8D, 0x0880);
798
799 /* Port E (MPC885 Reference Manual - 34.6) */
800 /*
801 * In/Out or per. Function 0/1
802 * PEDIR[31] = 0 [0x00000001] -> GPIO: (DONE_FPGA_FIRMWARE)
803 * PEDIR[29] = 1 [0x00000004] -> GPIO: (USB_SPEED)
804 * PEDIR[28] = 1 [0x00000008] -> GPIO: (USB_SUSPEND)
805 * PEDIR[25] = 0 [0x00000040] -> GPIO: (RXD4)
806 * PEDIR[24] = 0 [0x00000080] -> GPIO: (BRG01)
807 * PEDIR[20] = 0 [0x00000800] -> GPIO: (SMTXD2)
808 * PEDIR[17] = 0 [0x00004000] -> GPIO: (CLK5)
809 */
810 clrsetbits_be32(&cp->cp_pedir, 0x000048CD, 0x0000000C);
811
812 /*
813 * open drain or active output
814 * PEODR[31] = 0 [0x00000001] -> GPIO: (DONE_FPGA_FIRMWARE)
815 * PEODR[29] = 0 [0x00000004] -> GPIO: (USB_SPEED)
816 * PEODR[28] = 1 [0x00000008] -> GPIO: (USB_SUSPEND)
817 * PEODR[27] = 0 [0x00000010] -> GPIO: (R2_RXER)
818 * PEODR[26] = 0 [0x00000020] -> GPIO: (R2_CRS_DV)
819 * PEODR[25] = 0 [0x00000040] -> GPIO: (RXD4)
820 * PEODR[24] = 0 [0x00000080] -> GPIO: (BRG01)
821 * PEODR[23] = 0 [0x00000100] -> GPIO: (DONE_FPGA_RADIO)
822 * PEODR[22] = 0 [0x00000200] -> GPIO: (R2_RXD1)
823 * PEODR[21] = 0 [0x00000400] -> GPIO: (R2_RXD0)
824 * PEODR[20] = 0 [0x00000800] -> GPIO: (SMTXD2)
825 * PEODR[19] = 0 [0x00001000] -> GPIO: (R2_TXEN)
826 * PEODR[17] = 0 [0x00004000] -> GPIO: (CLK5)
827 * PEODR[16] = 0 [0x00008000] -> GPIO: (R2_REF_CLK)
828 */
829 clrsetbits_be32(&cp->cp_peodr, 0x0000DFFD, 0x00000008);
830
831 /*
832 * GPIO or per. Function
833 * PEPAR[31] = 0 [0x00000001] -> GPIO: (DONE_FPGA_FIRMWARE)
834 * PEPAR[30] = 0 [0x00000002] -> GPIO: (PROG_FPGA_FIRMWARE)
835 * PEPAR[29] = 0 [0x00000004] -> GPIO: (USB_SPEED)
836 * PEPAR[28] = 0 [0x00000008] -> GPIO: (USB_SUSPEND)
837 * PEPAR[18] = 0 [0x00002000] -> GPIO: (PROG_FPGA_RADIO)
838 */
839 clrbits_be32(&cp->cp_pepar, 0x0000200F);
840
841 /*
842 * Special Option register
843 * PESO[31] = 0 [0x00000001] -> GPIO: (DONE_FPGA_FIRMWARE)
844 * PESO[30] = 0 [0x00000002] -> GPIO: (PROG_FPGA_FIRMWARE)
845 * PESO[29] = 0 [0x00000004] -> GPIO: (USB_SPEED)
846 * PESO[28] = 0 [0x00000008] -> GPIO: (USB_SUSPEND)
847 * PESO[27] = 0 [0x00000010] -> GPIO: (R2_RXER)
848 * PESO[26] = 0 [0x00000020] -> GPIO: (R2_CRS_DV)
849 * PESO[25] = 0 [0x00000040] -> GPIO: (RXD4)
850 * PESO[22] = 0 [0x00000200] -> GPIO: (R2_RXD1)
851 * PESO[21] = 0 [0x00000400] -> GPIO: (R2_RXD0)
852 * PESO[18] = 0 [0x00002000] -> GPIO: (PROG_FPGA_RADIO)
853 * PESO[17] = 0 [0x00004000] -> GPIO: (CLK5)
854 * PESO[16] = 0 [0x00008000] -> GPIO: (R2_REF_CLK)
855 */
856 clrbits_be32(&cp->cp_peso, 0x0000E67F);
857
858 /* Is a motherboard present ? */
859 if (in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE) {
860 /* Initialize signal PROG_FPGA_FIRMWARE */
861 out_be32(&cp->cp_pedat, 0x00000002);
862 out_be32(&cp->cp_peodr, 0x00000002);
863 out_be32(&cp->cp_pedir, 0x00000002);
864
865 /* Check if fpga firmware is loaded */
866 if (!(in_be32(&cp->cp_pedat) & 0x00000001)) {
867 /* Load fpga firmware */
868 /* Activate PROG_FPGA_FIRMWARE for 1 usec */
869 clrbits_be32(&cp->cp_pedat, 0x00000002);
870 udelay(1);
871 setbits_be32(&cp->cp_pedat, 0x00000002);
872
873 /* Wait 200 msec and check DONE_FPGA_FIRMWARE */
874 mdelay(200);
875 if (!(in_be32(&cp->cp_pedat) & 0x00000001))
876 hang();
877
878 /* Send a reset signal and wait for 20 msec */
879 clrbits_be16(ADDR_CPLD_R_RESET, R_RST_STATUS);
880 mdelay(20);
881 setbits_be16(ADDR_CPLD_R_RESET, R_RST_STATUS);
882 }
883
884 /* Wait 300 msec and check the reset state */
885 mdelay(300);
886 if (!(in_be16(ADDR_CPLD_R_RESET) & R_RESET_STATUS))
887 hang();
888
889 iop_setup_common();
890 } else {
891 iop_setup_cmpc885();
892 }
893
894 return 0;
895 }
896