1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2010-2020 CS Group
4  * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
5  * Christophe Leroy <christophe.leroy@c-s.fr>
6  * Charles Frey <charles.frey@c-s.fr>
7  */
8 
9 #include <config.h>
10 #include <nand.h>
11 #include <linux/bitops.h>
12 #include <linux/mtd/rawnand.h>
13 #include <asm/io.h>
14 
15 #define BIT_CLE		BIT(3)
16 #define BIT_ALE		BIT(2)
17 #define BIT_NCE		BIT(0)
18 
nand_mask(unsigned int ctrl)19 static u32 nand_mask(unsigned int ctrl)
20 {
21 	return ((ctrl & NAND_CLE) ? BIT_CLE : 0) |
22 	       ((ctrl & NAND_ALE) ? BIT_ALE : 0) |
23 	       (!(ctrl & NAND_NCE) ? BIT_NCE : 0);
24 }
25 
nand_hwcontrol(struct mtd_info * mtdinfo,int cmd,unsigned int ctrl)26 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
27 {
28 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
29 	struct nand_chip *chip = mtd_to_nand(mtdinfo);
30 
31 	if (ctrl & NAND_CTRL_CHANGE)
32 		clrsetbits_be16(&immr->im_ioport.iop_pddat,
33 				BIT_CLE | BIT_ALE | BIT_NCE, nand_mask(ctrl));
34 
35 	if (cmd != NAND_CMD_NONE)
36 		out_8(chip->IO_ADDR_W, cmd);
37 }
38 
board_nand_init(struct nand_chip * chip)39 int board_nand_init(struct nand_chip *chip)
40 {
41 	chip->chip_delay	= 60;
42 	chip->ecc.mode		= NAND_ECC_SOFT;
43 	chip->cmd_ctrl		= nand_hwcontrol;
44 
45 	return 0;
46 }
47