1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2022 Marek Vasut <marex@denx.de>
4 */
5
6 #include <hang.h>
7 #include <image.h>
8 #include <init.h>
9 #include <spl.h>
10 #include <asm/io.h>
11 #include <asm-generic/gpio.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/ddr.h>
14 #include <asm/arch/imx8mp_pins.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/arch/ddr.h>
18 #include <asm/sections.h>
19
20 #include <dm/uclass.h>
21 #include <dm/device.h>
22 #include <dm/uclass-internal.h>
23 #include <dm/device-internal.h>
24
25 #include <linux/bitfield.h>
26
27 #include <power/pmic.h>
28 #include <power/pca9450.h>
29
30 #include "lpddr4_timing.h"
31
32 DECLARE_GLOBAL_DATA_PTR;
33
34 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
35 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
36
37 static const iomux_v3_cfg_t uart_pads[] = {
38 MX8MP_PAD_SAI2_RXFS__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
39 MX8MP_PAD_SAI2_RXC__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
40 };
41
42 static const iomux_v3_cfg_t wdog_pads[] = {
43 MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
44 };
45
46 static bool dh_gigabit_eqos, dh_gigabit_fec;
47 static u8 dh_som_rev;
48
dh_imx8mp_early_init_f(void)49 static void dh_imx8mp_early_init_f(void)
50 {
51 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
52
53 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
54
55 set_wdog_reset(wdog);
56
57 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
58 }
59
dh_imx8mp_board_power_init(void)60 static int dh_imx8mp_board_power_init(void)
61 {
62 struct udevice *dev;
63 int ret;
64
65 ret = pmic_get("pmic@25", &dev);
66 if (ret == -ENODEV) {
67 puts("Failed to get PMIC\n");
68 return 0;
69 }
70 if (ret != 0)
71 return ret;
72
73 /* BUCKxOUT_DVS0/1 control BUCK123 output. */
74 pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
75
76 /* Increase VDD_SOC to typical value 0.95V before first DRAM access. */
77 if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV))
78 /* Set DVS0 to 0.85V for special case. */
79 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
80 else
81 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c);
82
83 /* Set DVS1 to 0.85v for suspend. */
84 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
85
86 /*
87 * Enable DVS control through PMIC_STBY_REQ and
88 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H).
89 */
90 pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
91
92 /* Kernel uses OD/OD frequency for SoC. */
93
94 /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */
95 pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c);
96
97 /* DRAM Vdd1 always FPWM */
98 pmic_reg_write(dev, PCA9450_BUCK5CTRL, 0x0d);
99 /* DRAM Vdd2/Vddq always FPWM */
100 pmic_reg_write(dev, PCA9450_BUCK6CTRL, 0x0d);
101
102 /* Set LDO4 and CONFIG2 to enable the I2C level translator. */
103 pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59);
104 pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
105
106 return 0;
107 }
108
109 static struct dram_timing_info *dram_timing_info[8] = {
110 NULL, /* 512 MiB */
111 NULL, /* 1024 MiB */
112 NULL, /* 1536 MiB */
113 &dh_imx8mp_dhcom_dram_timing_16g_x32, /* 2048 MiB */
114 NULL, /* 3072 MiB */
115 &dh_imx8mp_dhcom_dram_timing_32g_x32, /* 4096 MiB */
116 NULL, /* 6144 MiB */
117 NULL, /* 8192 MiB */
118 };
119
spl_dram_init(void)120 static void spl_dram_init(void)
121 {
122 const u16 size[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 };
123 u8 memcfg = dh_get_memcfg();
124 int i;
125
126 printf("DDR: %d MiB [0x%x]\n", size[memcfg], memcfg);
127
128 if (!dram_timing_info[memcfg]) {
129 printf("Unsupported DRAM strapping, trying lowest supported. MEMCFG=0x%x\n",
130 memcfg);
131 for (i = 0; i < ARRAY_SIZE(dram_timing_info); i++)
132 if (dram_timing_info[i]) /* Configuration found */
133 break;
134 }
135
136 ddr_init(dram_timing_info[memcfg]);
137
138 printf("DDR: Inline ECC %sabled\n",
139 (readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK) ?
140 "en" : "dis");
141 }
142
143 #if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
144 static const scrub_func_t dram_scrub_fn[8] = {
145 NULL, /* 512 MiB */
146 NULL, /* 1024 MiB */
147 NULL, /* 1536 MiB */
148 dh_imx8mp_dhcom_dram_scrub_16g_x32, /* 2048 MiB */
149 NULL, /* 3072 MiB */
150 dh_imx8mp_dhcom_dram_scrub_32g_x32, /* 4096 MiB */
151 NULL, /* 6144 MiB */
152 NULL, /* 8192 MiB */
153 };
154
board_dram_ecc_scrub(void)155 void board_dram_ecc_scrub(void)
156 {
157 u8 memcfg = dh_get_memcfg();
158
159 if (!dram_scrub_fn[memcfg])
160 return;
161
162 dram_scrub_fn[memcfg]();
163 }
164 #endif
165
spl_board_init(void)166 void spl_board_init(void)
167 {
168 /*
169 * Set GIC clock to 500 MHz for OD VDD_SOC. Kernel driver does not
170 * allow to change it. Should set the clock after PMIC setting done.
171 * Default is 400 MHz (system_pll1_800m with div = 2) set by ROM for
172 * ND VDD_SOC.
173 */
174 clock_enable(CCGR_GIC, 0);
175 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
176 clock_enable(CCGR_GIC, 1);
177 }
178
spl_board_boot_device(enum boot_device boot_dev_spl)179 int spl_board_boot_device(enum boot_device boot_dev_spl)
180 {
181 return BOOT_DEVICE_BOOTROM;
182 }
183
board_spl_fit_append_fdt_skip(const char * name)184 int board_spl_fit_append_fdt_skip(const char *name)
185 {
186 if (!dh_gigabit_eqos) { /* 1x or 2x RMII PHY SoM */
187 if (dh_gigabit_fec) { /* 1x RMII PHY SoM */
188 if (!strcmp(name, "fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast"))
189 return 0;
190 } else { /* 2x RMII PHY SoM */
191 if (!strcmp(name, "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast"))
192 return 0;
193 if (!strcmp(name, "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast")) {
194 /* 2x RMII PHY SoM on PDK2 or PDK3 */
195 if (of_machine_is_compatible("dh,imx8mp-dhcom-pdk2") ||
196 of_machine_is_compatible("dh,imx8mp-dhcom-pdk3"))
197 return 0;
198 }
199 }
200 }
201
202 if (dh_som_rev == 0x0) { /* Prototype SoM rev.100 */
203 if (!strcmp(name, "fdt-dto-imx8mp-dhcom-som-overlay-rev100"))
204 return 0;
205
206 if (!strcmp(name, "fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100") &&
207 of_machine_is_compatible("dh,imx8mp-dhcom-pdk3"))
208 return 0;
209 }
210
211 return 1; /* Skip this DTO */
212 }
213
dh_imx8mp_board_cache_config(void)214 static void dh_imx8mp_board_cache_config(void)
215 {
216 const void __iomem *mux_base = (void __iomem *)IOMUXC_BASE_ADDR;
217 const u32 mux_sion[] = {
218 FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24),
219 FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI1_TXFS__GPIO4_IO10),
220 FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_NAND_DQS__GPIO3_IO14),
221 FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI1_TXD7__GPIO4_IO19),
222 FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI5_MCLK__GPIO3_IO25),
223 };
224 int i;
225
226 for (i = 0; i < ARRAY_SIZE(mux_sion); i++)
227 setbits_le32(mux_base + mux_sion[i], IOMUX_CONFIG_SION);
228
229 dh_gigabit_eqos = !(readl(GPIO1_BASE_ADDR) & BIT(24));
230 dh_gigabit_fec = !(readl(GPIO4_BASE_ADDR) & BIT(10));
231 dh_som_rev = !!(readl(GPIO3_BASE_ADDR) & BIT(14));
232 dh_som_rev |= !!(readl(GPIO4_BASE_ADDR) & BIT(19)) << 1;
233 dh_som_rev |= !!(readl(GPIO3_BASE_ADDR) & BIT(25)) << 2;
234
235 for (i = 0; i < ARRAY_SIZE(mux_sion); i++)
236 clrbits_le32(mux_base + mux_sion[i], IOMUX_CONFIG_SION);
237 }
238
board_init_f(ulong dummy)239 void board_init_f(ulong dummy)
240 {
241 struct udevice *dev;
242 int ret;
243
244 arch_cpu_init();
245
246 init_uart_clk(0);
247
248 dh_imx8mp_early_init_f();
249
250 preloader_console_init();
251
252 /* Clear the BSS. */
253 memset(__bss_start, 0, __bss_end - __bss_start);
254
255 ret = spl_early_init();
256 if (ret) {
257 debug("spl_early_init() failed: %d\n", ret);
258 hang();
259 }
260
261 ret = uclass_get_device_by_name(UCLASS_CLK,
262 "clock-controller@30380000",
263 &dev);
264 if (ret < 0) {
265 printf("Failed to find clock node. Check device tree\n");
266 hang();
267 }
268
269 enable_tzc380();
270
271 dh_imx8mp_board_power_init();
272
273 /* DDR initialization */
274 spl_dram_init();
275
276 dh_imx8mp_board_cache_config();
277
278 board_init_r(NULL, 0);
279 }
280