1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C)Copyright 2016 Rockchip Electronics Co., Ltd
4 * Authors: Andy Yan <andy.yan@rock-chips.com>
5 */
6
7 #include <init.h>
8 #include <syscon.h>
9 #include <asm/global_data.h>
10 #include <asm/arch-rockchip/clock.h>
11 #include <asm/arch-rockchip/grf_rv1108.h>
12 #include <asm/arch-rockchip/hardware.h>
13 #include <asm/gpio.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
board_early_init_f(void)17 int board_early_init_f(void)
18 {
19 struct rv1108_grf *grf;
20 enum {
21 GPIO3C3_SHIFT = 6,
22 GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
23
24 GPIO3C2_SHIFT = 4,
25 GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
26
27 GPIO2D2_SHIFT = 4,
28 GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
29 GPIO2D2_GPIO = 0,
30 GPIO2D2_UART2_SOUT_M0,
31
32 GPIO2D1_SHIFT = 2,
33 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
34 GPIO2D1_GPIO = 0,
35 GPIO2D1_UART2_SIN_M0,
36 };
37
38 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
39
40 /* Elgin board use UART2 m0 for debug*/
41 rk_clrsetreg(&grf->gpio2d_iomux,
42 GPIO2D2_MASK | GPIO2D1_MASK,
43 GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
44 GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
45 rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK);
46
47 return 0;
48 }
49
50 #define MODEM_ENABLE_GPIO 111
51
rk_board_late_init(void)52 int rk_board_late_init(void)
53 {
54 gpio_request(MODEM_ENABLE_GPIO, "modem_enable");
55 gpio_direction_output(MODEM_ENABLE_GPIO, 0);
56
57 return 0;
58 }
59
dram_init(void)60 int dram_init(void)
61 {
62 gd->ram_size = 0x8000000;
63
64 return 0;
65 }
66
dram_init_banksize(void)67 int dram_init_banksize(void)
68 {
69 gd->bd->bi_dram[0].start = 0x60000000;
70 gd->bd->bi_dram[0].size = 0x8000000;
71
72 return 0;
73 }
74