1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2022 Amarula Solutions(India)
4 * Copyright (C) 2016 Engicam S.r.l.
5 *
6 * Authors:
7 * Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
8 * Jagan Teki <jagan@amarulasolutions.com>
9 */
10
11 #include <hang.h>
12 #include <init.h>
13 #include <log.h>
14 #include <spl.h>
15 #include <asm/global_data.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/imx8mp_pins.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/gpio.h>
21 #include <asm/mach-imx/iomux-v3.h>
22 #include <asm/mach-imx/mxc_i2c.h>
23 #include <asm/arch/ddr.h>
24 #include <power/pmic.h>
25 #include <power/pca9450.h>
26
27 DECLARE_GLOBAL_DATA_PTR;
28
spl_board_boot_device(enum boot_device boot_dev_spl)29 int spl_board_boot_device(enum boot_device boot_dev_spl)
30 {
31 return BOOT_DEVICE_BOOTROM;
32 }
33
spl_dram_init(void)34 void spl_dram_init(void)
35 {
36 ddr_init(&dram_timing);
37 }
38
39 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
40 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
41 struct i2c_pads_info i2c_pad_info1 = {
42 .scl = {
43 .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
44 .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
45 .gp = IMX_GPIO_NR(5, 14),
46 },
47 .sda = {
48 .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
49 .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
50 .gp = IMX_GPIO_NR(5, 15),
51 },
52 };
53
54 #if CONFIG_IS_ENABLED(POWER_LEGACY)
55 #define I2C_PMIC 0
power_init_board(void)56 int power_init_board(void)
57 {
58 struct pmic *p;
59 int ret;
60
61 ret = power_pca9450_init(I2C_PMIC, 0x25);
62 if (ret)
63 printf("power init failed");
64 p = pmic_get("PCA9450");
65 pmic_probe(p);
66
67 /* BUCKxOUT_DVS0/1 control BUCK123 output */
68 pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
69
70 #ifdef CONFIG_IMX8M_LPDDR4
71 /*
72 * increase VDD_SOC to typical value 0.95V before first
73 * DRAM access, set DVS1 to 0.85v for suspend.
74 * Enable DVS control through PMIC_STBY_REQ and
75 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
76 */
77 #ifdef CONFIG_IMX8M_VDD_SOC_850MV
78 /* set DVS0 to 0.85v for special case*/
79 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
80 #else
81 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
82 #endif
83 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
84 pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
85
86 /* Kernel uses OD/OD freq for SOC */
87 /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
88 pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
89 #elif defined(CONFIG_IMX8M_DDR4)
90 /* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */
91 pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
92
93 /* Set NVCC_DRAM to 1.2v for DDR4 */
94 pmic_reg_write(p, PCA9450_BUCK6OUT, 0x18);
95 #endif
96
97 return 0;
98 }
99 #endif
100
spl_board_init(void)101 void spl_board_init(void)
102 {
103 /* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does not allow to change it.
104 * Should set the clock after PMIC setting done.
105 * Default is 400Mhz (system_pll1_800m with div = 2) set by ROM for ND VDD_SOC
106 */
107 clock_enable(CCGR_GIC, 0);
108 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
109 clock_enable(CCGR_GIC, 1);
110
111 puts("Normal Boot\n");
112 }
113
114 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)115 int board_fit_config_name_match(const char *name)
116 {
117 /* Just empty function now - can't decide what to choose */
118 debug("%s: %s\n", __func__, name);
119
120 return 0;
121 }
122 #endif
123
board_init_f(ulong dummy)124 void board_init_f(ulong dummy)
125 {
126 int ret;
127
128 arch_cpu_init();
129
130 init_uart_clk(1);
131
132 ret = spl_early_init();
133 if (ret) {
134 debug("spl_early_init() failed: %d\n", ret);
135 hang();
136 }
137
138 preloader_console_init();
139
140 enable_tzc380();
141
142 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
143
144 power_init_board();
145
146 /* DDR initialization */
147 spl_dram_init();
148 }
149