1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 */
5
6 #include <fsl_ddr_sdram.h>
7 #include <fsl_ddr_dimm_params.h>
8 #include <asm/global_data.h>
9 #include "ddr.h"
10 #ifdef CONFIG_FSL_DEEP_SLEEP
11 #include <fsl_sleep.h>
12 #endif
13 #include <log.h>
14 #include <asm/arch/clock.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)18 void fsl_ddr_board_options(memctl_options_t *popts,
19 dimm_params_t *pdimm,
20 unsigned int ctrl_num)
21 {
22 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
23 ulong ddr_freq;
24
25 if (ctrl_num > 1) {
26 printf("Not supported controller number %d\n", ctrl_num);
27 return;
28 }
29 if (!pdimm->n_ranks)
30 return;
31
32 if (popts->registered_dimm_en)
33 pbsp = rdimms[0];
34 else
35 pbsp = udimms[0];
36
37 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
38 * freqency and n_banks specified in board_specific_parameters table.
39 */
40 ddr_freq = get_ddr_freq(0) / 1000000;
41 while (pbsp->datarate_mhz_high) {
42 if (pbsp->n_ranks == pdimm->n_ranks) {
43 if (ddr_freq <= pbsp->datarate_mhz_high) {
44 popts->clk_adjust = pbsp->clk_adjust;
45 popts->wrlvl_start = pbsp->wrlvl_start;
46 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
47 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
48 goto found;
49 }
50 pbsp_highest = pbsp;
51 }
52 pbsp++;
53 }
54
55 if (pbsp_highest) {
56 printf("Error: board specific timing not found for %lu MT/s\n",
57 ddr_freq);
58 printf("Trying to use the highest speed (%u) parameters\n",
59 pbsp_highest->datarate_mhz_high);
60 popts->clk_adjust = pbsp_highest->clk_adjust;
61 popts->wrlvl_start = pbsp_highest->wrlvl_start;
62 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
63 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
64 } else {
65 panic("DIMM is not supported by this board");
66 }
67 found:
68 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
69 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
70
71 popts->data_bus_width = 0; /* 64-bit data bus */
72 popts->bstopre = 0; /* enable auto precharge */
73
74 /*
75 * Factors to consider for half-strength driver enable:
76 * - number of DIMMs installed
77 */
78 popts->half_strength_driver_enable = 0;
79 /*
80 * Write leveling override
81 */
82 popts->wrlvl_override = 1;
83 popts->wrlvl_sample = 0xf;
84
85 /*
86 * Rtt and Rtt_WR override
87 */
88 popts->rtt_override = 0;
89
90 /* Enable ZQ calibration */
91 popts->zq_en = 1;
92
93 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
94 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
95 DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
96
97 /* optimize cpo for erratum A-009942 */
98 popts->cpo_sample = 0x61;
99 }
100
101 #ifdef CONFIG_TFABOOT
fsl_initdram(void)102 int fsl_initdram(void)
103 {
104 gd->ram_size = tfa_get_dram_size();
105
106 if (!gd->ram_size)
107 gd->ram_size = fsl_ddr_sdram_size();
108
109 return 0;
110 }
111 #else
fsl_initdram(void)112 int fsl_initdram(void)
113 {
114 phys_size_t dram_size;
115
116 #if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD)
117 gd->ram_size = fsl_ddr_sdram_size();
118
119 return 0;
120 #else
121 puts("Initializing DDR....using SPD\n");
122
123 dram_size = fsl_ddr_sdram();
124 #endif
125
126 erratum_a008850_post();
127
128 gd->ram_size = dram_size;
129
130 return 0;
131 }
132 #endif
133