1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Freescale Semiconductor
4 * Copyright 2021 NXP
5 */
6 #include <config.h>
7 #include <clock_legacy.h>
8 #include <display_options.h>
9 #include <env.h>
10 #include <init.h>
11 #include <malloc.h>
12 #include <errno.h>
13 #include <netdev.h>
14 #include <fsl_ifc.h>
15 #include <fsl_ddr.h>
16 #include <asm/global_data.h>
17 #include <asm/io.h>
18 #include <fdt_support.h>
19 #include <linux/libfdt.h>
20 #include <fsl-mc/fsl_mc.h>
21 #include <env_internal.h>
22 #include <i2c.h>
23 #include <rtc.h>
24 #include <asm/arch/soc.h>
25 #include <hwconfig.h>
26 #include <asm/arch-fsl-layerscape/fsl_icid.h>
27 #include "../common/i2c_mux.h"
28
29 #include "../common/qixis.h"
30 #include "ls2080aqds_qixis.h"
31 #include "../common/vid.h"
32
33 #define PIN_MUX_SEL_SDHC 0x00
34 #define PIN_MUX_SEL_DSPI 0x0a
35 #define SCFG_QSPICLKCTRL_DIV_20 (5 << 27)
36
37 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
38
39 DECLARE_GLOBAL_DATA_PTR;
40
41 enum {
42 MUX_TYPE_SDHC,
43 MUX_TYPE_DSPI,
44 };
45
get_qixis_addr(void)46 unsigned long long get_qixis_addr(void)
47 {
48 unsigned long long addr;
49
50 if (gd->flags & GD_FLG_RELOC)
51 addr = QIXIS_BASE_PHYS;
52 else
53 addr = QIXIS_BASE_PHYS_EARLY;
54
55 /*
56 * IFC address under 256MB is mapped to 0x30000000, any address above
57 * is mapped to 0x5_10000000 up to 4GB.
58 */
59 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
60
61 return addr;
62 }
63
checkboard(void)64 int checkboard(void)
65 {
66 char buf[64];
67 u8 sw;
68 static const char *const freq[] = {"100", "125", "156.25",
69 "100 separate SSCG"};
70 int clock;
71
72 cpu_name(buf);
73 printf("Board: %s-QDS, ", buf);
74
75 sw = QIXIS_READ(arch);
76 printf("Board Arch: V%d, ", sw >> 4);
77 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
78
79 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
80
81 sw = QIXIS_READ(brdcfg[0]);
82 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
83
84 if (sw < 0x8)
85 printf("vBank: %d\n", sw);
86 else if (sw == 0x8)
87 puts("PromJet\n");
88 else if (sw == 0x9)
89 puts("NAND\n");
90 else if (sw == 0xf)
91 puts("QSPI\n");
92 else if (sw == 0x15)
93 printf("IFCCard\n");
94 else
95 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
96
97 printf("FPGA: v%d (%s), build %d",
98 (int)QIXIS_READ(scver), qixis_read_tag(buf),
99 (int)qixis_read_minor());
100 /* the timestamp string contains "\n" at the end */
101 printf(" on %s", qixis_read_time(buf));
102
103 /*
104 * Display the actual SERDES reference clocks as configured by the
105 * dip switches on the board. Note that the SWx registers could
106 * technically be set to force the reference clocks to match the
107 * values that the SERDES expects (or vice versa). For now, however,
108 * we just display both values and hope the user notices when they
109 * don't match.
110 */
111 puts("SERDES1 Reference : ");
112 sw = QIXIS_READ(brdcfg[2]);
113 clock = (sw >> 6) & 3;
114 printf("Clock1 = %sMHz ", freq[clock]);
115 clock = (sw >> 4) & 3;
116 printf("Clock2 = %sMHz", freq[clock]);
117
118 puts("\nSERDES2 Reference : ");
119 clock = (sw >> 2) & 3;
120 printf("Clock1 = %sMHz ", freq[clock]);
121 clock = (sw >> 0) & 3;
122 printf("Clock2 = %sMHz\n", freq[clock]);
123
124 return 0;
125 }
126
get_board_sys_clk(void)127 unsigned long get_board_sys_clk(void)
128 {
129 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
130
131 switch (sysclk_conf & 0x0F) {
132 case QIXIS_SYSCLK_83:
133 return 83333333;
134 case QIXIS_SYSCLK_100:
135 return 100000000;
136 case QIXIS_SYSCLK_125:
137 return 125000000;
138 case QIXIS_SYSCLK_133:
139 return 133333333;
140 case QIXIS_SYSCLK_150:
141 return 150000000;
142 case QIXIS_SYSCLK_160:
143 return 160000000;
144 case QIXIS_SYSCLK_166:
145 return 166666666;
146 }
147 return 66666666;
148 }
149
get_board_ddr_clk(void)150 unsigned long get_board_ddr_clk(void)
151 {
152 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
153
154 switch ((ddrclk_conf & 0x30) >> 4) {
155 case QIXIS_DDRCLK_100:
156 return 100000000;
157 case QIXIS_DDRCLK_125:
158 return 125000000;
159 case QIXIS_DDRCLK_133:
160 return 133333333;
161 }
162 return 66666666;
163 }
164
config_board_mux(int ctrl_type)165 int config_board_mux(int ctrl_type)
166 {
167 u8 reg5;
168
169 reg5 = QIXIS_READ(brdcfg[5]);
170
171 switch (ctrl_type) {
172 case MUX_TYPE_SDHC:
173 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
174 break;
175 case MUX_TYPE_DSPI:
176 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
177 break;
178 default:
179 printf("Wrong mux interface type\n");
180 return -1;
181 }
182
183 QIXIS_WRITE(brdcfg[5], reg5);
184
185 return 0;
186 }
187
board_init(void)188 int board_init(void)
189 {
190 char *env_hwconfig;
191 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
192 u32 val;
193
194 init_final_memctl_regs();
195
196 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
197
198 env_hwconfig = env_get("hwconfig");
199
200 if (hwconfig_f("dspi", env_hwconfig) &&
201 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
202 config_board_mux(MUX_TYPE_DSPI);
203 else
204 config_board_mux(MUX_TYPE_SDHC);
205
206 #if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_FSL_QSPI)
207 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
208
209 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
210 QIXIS_WRITE(brdcfg[9],
211 (QIXIS_READ(brdcfg[9]) & 0xf8) |
212 FSL_QIXIS_BRDCFG9_QSPI);
213 #endif
214
215 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
216
217 #ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
218 #if CONFIG_IS_ENABLED(DM_I2C)
219 rtc_enable_32khz_output(0, CFG_SYS_I2C_RTC_ADDR);
220 #else
221 rtc_enable_32khz_output();
222 #endif
223 #endif
224
225 #if !defined(CONFIG_SYS_EARLY_PCI_INIT)
226 pci_init();
227 #endif
228
229 return 0;
230 }
231
board_early_init_f(void)232 int board_early_init_f(void)
233 {
234 #if defined(CONFIG_SYS_I2C_EARLY_INIT)
235 i2c_early_init_f();
236 #endif
237 fsl_lsch3_early_init_f();
238 #ifdef CONFIG_FSL_QSPI
239 /* input clk: 1/2 platform clk, output: input/20 */
240 out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
241 #endif
242 return 0;
243 }
244
misc_init_r(void)245 int misc_init_r(void)
246 {
247 if (adjust_vdd(0))
248 printf("Warning: Adjusting core voltage failed.\n");
249
250 return 0;
251 }
252
detail_board_ddr_info(void)253 void detail_board_ddr_info(void)
254 {
255 puts("\nDDR ");
256 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
257 print_ddr_info(0);
258 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
259 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
260 puts("\nDP-DDR ");
261 print_size(gd->bd->bi_dram[2].size, "");
262 print_ddr_info(CONFIG_DP_DDR_CTRL);
263 }
264 #endif
265 }
266
267 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD)
fdt_fixup_board_enet(void * fdt)268 void fdt_fixup_board_enet(void *fdt)
269 {
270 int offset;
271
272 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
273
274 if (offset < 0)
275 offset = fdt_path_offset(fdt, "/fsl-mc");
276
277 if (offset < 0) {
278 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
279 __func__, offset);
280 return;
281 }
282
283 if (get_mc_boot_status() == 0 &&
284 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
285 fdt_status_okay(fdt, offset);
286 else
287 fdt_status_fail(fdt, offset);
288 }
289
board_quiesce_devices(void)290 void board_quiesce_devices(void)
291 {
292 fsl_mc_ldpaa_exit(gd->bd);
293 }
294 #endif
295
296 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,struct bd_info * bd)297 int ft_board_setup(void *blob, struct bd_info *bd)
298 {
299 u64 base[CONFIG_NR_DRAM_BANKS];
300 u64 size[CONFIG_NR_DRAM_BANKS];
301
302 ft_cpu_setup(blob, bd);
303
304 /* fixup DT for the two GPP DDR banks */
305 base[0] = gd->bd->bi_dram[0].start;
306 size[0] = gd->bd->bi_dram[0].size;
307 base[1] = gd->bd->bi_dram[1].start;
308 size[1] = gd->bd->bi_dram[1].size;
309
310 #ifdef CONFIG_RESV_RAM
311 /* reduce size if reserved memory is within this bank */
312 if (gd->arch.resv_ram >= base[0] &&
313 gd->arch.resv_ram < base[0] + size[0])
314 size[0] = gd->arch.resv_ram - base[0];
315 else if (gd->arch.resv_ram >= base[1] &&
316 gd->arch.resv_ram < base[1] + size[1])
317 size[1] = gd->arch.resv_ram - base[1];
318 #endif
319
320 fdt_fixup_memory_banks(blob, base, size, 2);
321
322 fdt_fsl_mc_fixup_iommu_map_entry(blob);
323
324 fsl_fdt_fixup_dr_usb(blob, bd);
325
326 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD)
327 fdt_fixup_board_enet(blob);
328 fdt_reserve_mc_mem(blob, 0x300);
329 #endif
330
331 fdt_fixup_icid(blob);
332
333 return 0;
334 }
335 #endif
336
qixis_dump_switch(void)337 void qixis_dump_switch(void)
338 {
339 int i, nr_of_cfgsw;
340
341 QIXIS_WRITE(cms[0], 0x00);
342 nr_of_cfgsw = QIXIS_READ(cms[1]);
343
344 puts("DIP switch settings dump:\n");
345 for (i = 1; i <= nr_of_cfgsw; i++) {
346 QIXIS_WRITE(cms[0], i);
347 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
348 }
349 }
350