1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2004
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 */
6
7 #include <config.h>
8 #include <command.h>
9 #include <init.h>
10 #include <malloc.h>
11 #include <asm/global_data.h>
12 #include <asm/immap.h>
13 #include <linux/delay.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
checkboard(void)17 int checkboard (void) {
18 ulong val;
19 uchar val8;
20
21 puts ("Board: ");
22 puts("Freescale M5249EVB");
23 val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
24 printf(" (Switch=%1X)\n", val8);
25
26 /*
27 * Set LED on
28 */
29 val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_SYS_GPIO1_LED;
30 mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */
31
32 return 0;
33 };
34
dram_init(void)35 int dram_init(void)
36 {
37 unsigned long junk = 0xa5a59696;
38
39 /*
40 * Note:
41 * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
42 */
43
44 #ifdef CFG_SYS_FAST_CLK
45 /*
46 * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
47 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
48 */
49 mbar_writeShort(MCFSIM_DCR, 0x8239);
50 #elif CFG_SYS_PLL_BYPASS
51 /*
52 * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
53 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
54 */
55 mbar_writeShort(MCFSIM_DCR, 0x8202);
56 #else
57 /*
58 * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
59 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
60 */
61 mbar_writeShort(MCFSIM_DCR, 0x8222);
62 #endif
63
64 /*
65 * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
66 * PM=1 (continuous page mode)
67 */
68
69 /* RE=0 (keep auto-refresh disabled while setting up registers) */
70 mbar_writeLong(MCFSIM_DACR0, 0x00003324);
71
72 /* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
73 mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
74
75 /** Precharge sequence **/
76 mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
77 *((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */
78 udelay(0x10); /* Allow several Precharge cycles */
79
80 /** Refresh Sequence **/
81 mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
82 udelay(0x7d0); /* Allow gobs of refresh cycles */
83
84 /** Mode Register initialization **/
85 mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
86 *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
87
88 gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
89
90 return 0;
91 };
92
testdram(void)93 int testdram(void)
94 {
95 /* TODO: XXX XXX XXX */
96 printf ("DRAM test not implemented!\n");
97
98 return (0);
99 }
100