1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2021 Gateworks Corporation
4 */
5
6 #include <env.h>
7 #include <fdt_support.h>
8 #include <init.h>
9 #include <led.h>
10 #include <mmc.h>
11 #include <miiphy.h>
12 #include <mmc.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/mach-imx/boot_mode.h>
16
17 #include "eeprom.h"
18 #include "../fsa.h"
19
board_phys_sdram_size(phys_size_t * size)20 int board_phys_sdram_size(phys_size_t *size)
21 {
22 if (!size)
23 return -EINVAL;
24
25 *size = get_ram_size((void *)PHYS_SDRAM, (long)PHYS_SDRAM_SIZE + (long)PHYS_SDRAM_2_SIZE);
26
27 return 0;
28 }
29
board_fit_config_name_match(const char * path)30 int board_fit_config_name_match(const char *path)
31 {
32 const char *name = path + strlen("freescale/");
33 static char init;
34 const char *dtb;
35 char buf[32];
36 int i = 0;
37
38 do {
39 dtb = eeprom_get_dtb_name(i++, buf, sizeof(buf));
40 if (!strcmp(dtb, name)) {
41 if (!init++)
42 printf("DTB : %s\n", name);
43 return 0;
44 }
45 } while (dtb);
46
47 return -1;
48 }
49
50 #if (IS_ENABLED(CONFIG_NET))
board_phy_config(struct phy_device * phydev)51 int board_phy_config(struct phy_device *phydev)
52 {
53 unsigned short val;
54
55 switch (phydev->phy_id) {
56 case 0x2000a231: /* TI DP83867 GbE PHY */
57 puts("DP83867 ");
58 /* LED configuration */
59 val = 0;
60 val |= 0x5 << 4; /* LED1(Amber;Speed) : 1000BT link */
61 val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
62 phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
63 break;
64 case 0xd565a401: /* MaxLinear GPY111 */
65 puts("GPY111 ");
66 break;
67 }
68
69 if (phydev->drv->config)
70 phydev->drv->config(phydev);
71
72 return 0;
73 }
74 #endif // IS_ENABLED(CONFIG_NET)
75
board_init(void)76 int board_init(void)
77 {
78 venice_eeprom_init(1);
79
80 /* detect and configure FSA adapters */
81 fsa_init();
82
83 return 0;
84 }
85
board_late_init(void)86 int board_late_init(void)
87 {
88 const char *str;
89 struct mmc *mmc = NULL;
90 char env[32];
91 int ret, i;
92 u8 enetaddr[6];
93 char fdt[64];
94 int bootdev;
95
96 /* Set board serial/model */
97 if (!env_get("serial#"))
98 env_set_ulong("serial#", eeprom_get_serial());
99 env_set("model", eeprom_get_model());
100
101 /* Set fdt_file vars */
102 i = 0;
103 do {
104 str = eeprom_get_dtb_name(i, fdt, sizeof(fdt));
105 if (str) {
106 sprintf(env, "fdt_file%d", i + 1);
107 strcat(fdt, ".dtb");
108 env_set(env, fdt);
109 }
110 i++;
111 } while (str);
112
113 /* Set mac addrs */
114 i = 0;
115 do {
116 if (i)
117 sprintf(env, "eth%daddr", i);
118 else
119 sprintf(env, "ethaddr");
120 str = env_get(env);
121 if (!str) {
122 ret = eeprom_getmac(i, enetaddr);
123 if (!ret)
124 eth_env_set_enetaddr(env, enetaddr);
125 }
126 i++;
127 } while (!ret);
128
129 /*
130 * set bootdev/bootblk/bootpart (used in firmware_update script)
131 * dynamically depending on boot device and SoC
132 */
133 bootdev = -1;
134 switch (get_boot_device()) {
135 case SD1_BOOT:
136 case MMC1_BOOT: /* SDHC1 */
137 bootdev = 0;
138 break;
139 case SD2_BOOT:
140 case MMC2_BOOT: /* SDHC2 */
141 bootdev = 1;
142 break;
143 case SD3_BOOT:
144 case MMC3_BOOT: /* SDHC3 */
145 bootdev = 2;
146 break;
147 default:
148 bootdev = 2; /* assume SDHC3 (eMMC) if booting over SDP */
149 break;
150 }
151 if (bootdev != -1)
152 mmc = find_mmc_device(bootdev);
153 if (mmc) {
154 int bootblk;
155
156 if (IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP))
157 bootblk = 32 * SZ_1K / 512;
158 else
159 bootblk = 33 * SZ_1K / 512;
160 mmc_init(mmc);
161 if (!IS_SD(mmc)) {
162 int bootpart;
163
164 switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
165 case EMMC_BOOT_PART_BOOT1:
166 bootpart = EMMC_HWPART_BOOT1;
167 break;
168 case EMMC_BOOT_PART_BOOT2:
169 bootpart = EMMC_HWPART_BOOT2;
170 break;
171 case EMMC_BOOT_PART_USER:
172 default:
173 bootpart = EMMC_HWPART_DEFAULT;
174 break;
175 }
176 /* IMX8MP/IMX8MN BOOTROM v2 uses offset=0 for boot parts */
177 if ((IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP)) &&
178 (bootpart == EMMC_BOOT_PART_BOOT1 || bootpart == EMMC_BOOT_PART_BOOT2))
179 bootblk = 0;
180 env_set_hex("bootpart", bootpart);
181 env_set_hex("bootblk", bootblk);
182 } else { /* SD */
183 env_set("bootpart", "");
184 env_set_hex("bootblk", bootblk);
185 }
186 env_set_hex("dev", bootdev);
187 }
188
189 /* override soc=imx8m to provide a more specific soc name */
190 if (IS_ENABLED(CONFIG_IMX8MN))
191 env_set("soc", "imx8mn");
192 else if (IS_ENABLED(CONFIG_IMX8MP))
193 env_set("soc", "imx8mp");
194 else if (IS_ENABLED(CONFIG_IMX8MM))
195 env_set("soc", "imx8mm");
196
197 return 0;
198 }
199
board_mmc_get_env_dev(int devno)200 int board_mmc_get_env_dev(int devno)
201 {
202 return devno;
203 }
204
mmc_get_env_part(struct mmc * mmc)205 uint mmc_get_env_part(struct mmc *mmc)
206 {
207 if (!IS_SD(mmc)) {
208 switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
209 case EMMC_BOOT_PART_BOOT1:
210 return EMMC_HWPART_BOOT1;
211 case EMMC_BOOT_PART_BOOT2:
212 return EMMC_HWPART_BOOT2;
213 }
214 }
215
216 return 0;
217 }
218
ft_board_setup(void * fdt,struct bd_info * bd)219 int ft_board_setup(void *fdt, struct bd_info *bd)
220 {
221 const char *base_model = eeprom_get_baseboard_model();
222 const char *path;
223 char pcbrev;
224 int off;
225
226 /* set board model dt prop */
227 fdt_setprop_string(fdt, 0, "board", eeprom_get_model());
228
229 /* fixups for FSA adapters */
230 fsa_ft_fixup(fdt);
231
232 if (!strncmp(base_model, "GW73", 4)) {
233 pcbrev = get_pcb_rev(base_model);
234 path = fdt_get_alias(fdt, "ethernet1");
235
236 if (pcbrev > 'B' && pcbrev < 'E' && path && !strncmp(path, "/soc@0/pcie@", 12)) {
237 printf("adjusting %s pcie\n", base_model);
238 /*
239 * revC/D/E has PCIe 4-port switch which changes
240 * ethernet1 PCIe GbE:
241 * from: pcie@0,0/pcie@1,0/pcie@2,4/pcie@6.0
242 * to: pcie@0,0/pcie@1,0/pcie@2,3/pcie@5.0
243 */
244 off = fdt_path_offset(fdt, "ethernet1");
245 if (off > 0) {
246 u32 reg[5];
247
248 fdt_set_name(fdt, off, "pcie@5,0");
249 off = fdt_parent_offset(fdt, off);
250 fdt_set_name(fdt, off, "pcie@2,3");
251 memset(reg, 0, sizeof(reg));
252 reg[0] = cpu_to_fdt32(PCI_DEVFN(3, 0));
253 fdt_setprop(fdt, off, "reg", reg, sizeof(reg));
254 }
255 }
256 }
257
258 return 0;
259 }
260