1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2014
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
5 */
6
7 #ifdef CONFIG_GDSYS_LEGACY_DRIVERS
8
9 #include <gdsys_fpga.h>
10 #include <linux/bitops.h>
11
12 enum pcb_video_type {
13 PCB_DVI_SL,
14 PCB_DP_165MPIX,
15 PCB_DP_300MPIX,
16 PCB_HDMI,
17 PCB_DP_1_2,
18 PCB_HDMI_2_0,
19 };
20
21 enum pcb_transmission_type {
22 PCB_CAT_1G,
23 PCB_FIBER_3G,
24 PCB_CAT_10G,
25 PCB_FIBER_10G,
26 };
27
28 enum carrier_speed {
29 CARRIER_SPEED_1G,
30 CARRIER_SPEED_3G,
31 CARRIER_SPEED_2_5G = CARRIER_SPEED_3G,
32 CARRIER_SPEED_10G,
33 };
34
35 enum ram_config {
36 RAM_DDR2_32BIT_295MBPS,
37 RAM_DDR3_32BIT_590MBPS,
38 RAM_DDR3_48BIT_590MBPS,
39 RAM_DDR3_64BIT_1800MBPS,
40 RAM_DDR3_48BIT_1800MBPS,
41 };
42
43 enum sysclock {
44 SYSCLK_147456,
45 };
46
47 struct fpga_versions {
48 bool video_channel;
49 bool con_side;
50 enum pcb_video_type pcb_video_type;
51 enum pcb_transmission_type pcb_transmission_type;
52 unsigned int hw_version;
53 };
54
55 struct fpga_features {
56 u8 video_channels;
57 u8 carriers;
58 enum carrier_speed carrier_speed;
59 enum ram_config ram_config;
60 enum sysclock sysclock;
61
62 bool pcm_tx;
63 bool pcm_rx;
64 bool spdif_tx;
65 bool spdif_rx;
66 bool usb2;
67 bool rs232;
68 bool compression_type1;
69 bool compression_type2;
70 bool compression_type3;
71 bool interlace;
72 bool osd;
73 bool compression_pipes;
74 };
75
76 #ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM
77
get_versions(unsigned int fpga,struct fpga_versions * versions)78 static int get_versions(unsigned int fpga, struct fpga_versions *versions)
79 {
80 enum {
81 VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12),
82 VERSIONS_FPGA_CON_SIDE = BIT(13),
83 VERSIONS_FPGA_SC = BIT(14),
84 VERSIONS_PCB_CON = BIT(9),
85 VERSIONS_PCB_SC = BIT(8),
86 VERSIONS_PCB_VIDEO_MASK = 0x3 << 6,
87 VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6,
88 VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6,
89 VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4,
90 VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4,
91 VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4,
92 VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4,
93 VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4,
94 VERSIONS_HW_VER_MASK = 0xf << 0,
95 };
96 u16 raw_versions;
97
98 memset(versions, 0, sizeof(struct fpga_versions));
99
100 FPGA_GET_REG(fpga, versions, &raw_versions);
101
102 versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL;
103 versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE;
104
105 switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) {
106 case VERSIONS_PCB_VIDEO_DP_1_2:
107 versions->pcb_video_type = PCB_DP_1_2;
108 break;
109
110 case VERSIONS_PCB_VIDEO_HDMI_2_0:
111 versions->pcb_video_type = PCB_HDMI_2_0;
112 break;
113 }
114
115 switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) {
116 case VERSIONS_PCB_TRANSMISSION_FIBER_10G:
117 versions->pcb_transmission_type = PCB_FIBER_10G;
118 break;
119
120 case VERSIONS_PCB_TRANSMISSION_CAT_10G:
121 versions->pcb_transmission_type = PCB_CAT_10G;
122 break;
123
124 case VERSIONS_PCB_TRANSMISSION_FIBER_3G:
125 versions->pcb_transmission_type = PCB_FIBER_3G;
126 break;
127
128 case VERSIONS_PCB_TRANSMISSION_CAT_1G:
129 versions->pcb_transmission_type = PCB_CAT_1G;
130 break;
131
132 }
133
134 versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
135
136 return 0;
137 }
138
get_features(unsigned int fpga,struct fpga_features * features)139 static int get_features(unsigned int fpga, struct fpga_features *features)
140 {
141 enum {
142 FEATURE_SPDIF_RX = BIT(15),
143 FEATURE_SPDIF_TX = BIT(14),
144 FEATURE_PCM_RX = BIT(13),
145 FEATURE_PCM_TX = BIT(12),
146 FEATURE_RAM_MASK = GENMASK(11, 8),
147 FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8,
148 FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8,
149 FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8,
150 FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8,
151 FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8,
152 FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6),
153 FEATURE_CARRIER_SPEED_1G = 0x0 << 6,
154 FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6,
155 FEATURE_CARRIER_SPEED_10G = 0x2 << 6,
156 FEATURE_CARRIERS_MASK = GENMASK(5, 4),
157 FEATURE_CARRIERS_0 = 0x0 << 4,
158 FEATURE_CARRIERS_1 = 0x1 << 4,
159 FEATURE_CARRIERS_2 = 0x2 << 4,
160 FEATURE_CARRIERS_4 = 0x3 << 4,
161 FEATURE_USB2 = BIT(3),
162 FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0),
163 FEATURE_VIDEOCHANNELS_0 = 0x0 << 0,
164 FEATURE_VIDEOCHANNELS_1 = 0x1 << 0,
165 FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0,
166 FEATURE_VIDEOCHANNELS_2 = 0x3 << 0,
167 };
168
169 enum {
170 EXT_FEATURE_OSD = BIT(15),
171 EXT_FEATURE_ETHERNET = BIT(9),
172 EXT_FEATURE_INTERLACE = BIT(8),
173 EXT_FEATURE_RS232 = BIT(7),
174 EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4),
175 EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4,
176 EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4,
177 EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4,
178 EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0),
179 EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1),
180 EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2),
181 };
182
183 u16 raw_features;
184 u16 raw_extended_features;
185
186 memset(features, 0, sizeof(struct fpga_features));
187
188 FPGA_GET_REG(fpga, fpga_features, &raw_features);
189 FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
190
191 switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) {
192 case FEATURE_VIDEOCHANNELS_0:
193 features->video_channels = 0;
194 break;
195
196 case FEATURE_VIDEOCHANNELS_1:
197 features->video_channels = 1;
198 break;
199
200 case FEATURE_VIDEOCHANNELS_1_1:
201 case FEATURE_VIDEOCHANNELS_2:
202 features->video_channels = 2;
203 break;
204 };
205
206 switch (raw_features & FEATURE_CARRIERS_MASK) {
207 case FEATURE_CARRIERS_0:
208 features->carriers = 0;
209 break;
210
211 case FEATURE_CARRIERS_1:
212 features->carriers = 1;
213 break;
214
215 case FEATURE_CARRIERS_2:
216 features->carriers = 2;
217 break;
218
219 case FEATURE_CARRIERS_4:
220 features->carriers = 4;
221 break;
222 }
223
224 switch (raw_features & FEATURE_CARRIER_SPEED_MASK) {
225 case FEATURE_CARRIER_SPEED_1G:
226 features->carrier_speed = CARRIER_SPEED_1G;
227 break;
228 case FEATURE_CARRIER_SPEED_2_5G:
229 features->carrier_speed = CARRIER_SPEED_2_5G;
230 break;
231 case FEATURE_CARRIER_SPEED_10G:
232 features->carrier_speed = CARRIER_SPEED_10G;
233 break;
234 }
235
236 switch (raw_features & FEATURE_RAM_MASK) {
237 case FEATURE_RAM_DDR2_32BIT_295MBPS:
238 features->ram_config = RAM_DDR2_32BIT_295MBPS;
239 break;
240
241 case FEATURE_RAM_DDR3_32BIT_590MBPS:
242 features->ram_config = RAM_DDR3_32BIT_590MBPS;
243 break;
244
245 case FEATURE_RAM_DDR3_48BIT_590MBPS:
246 features->ram_config = RAM_DDR3_48BIT_590MBPS;
247 break;
248
249 case FEATURE_RAM_DDR3_64BIT_1800MBPS:
250 features->ram_config = RAM_DDR3_64BIT_1800MBPS;
251 break;
252
253 case FEATURE_RAM_DDR3_48BIT_1800MBPS:
254 features->ram_config = RAM_DDR3_48BIT_1800MBPS;
255 break;
256 }
257
258 features->pcm_tx = raw_features & FEATURE_PCM_TX;
259 features->pcm_rx = raw_features & FEATURE_PCM_RX;
260 features->spdif_tx = raw_features & FEATURE_SPDIF_TX;
261 features->spdif_rx = raw_features & FEATURE_SPDIF_RX;
262 features->usb2 = raw_features & FEATURE_USB2;
263 features->rs232 = raw_extended_features & EXT_FEATURE_RS232;
264 features->compression_type1 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE1;
265 features->compression_type2 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE2;
266 features->compression_type3 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE3;
267 features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE;
268 features->osd = raw_extended_features & EXT_FEATURE_OSD;
269 features->compression_pipes = raw_extended_features & EXT_FEATURE_COMPRESSION_PERF_MASK;
270
271 return 0;
272 }
273
274 #else
275
get_versions(unsigned int fpga,struct fpga_versions * versions)276 static int get_versions(unsigned int fpga, struct fpga_versions *versions)
277 {
278 enum {
279 /* HW version encoding is a mess, leave it for the moment */
280 VERSIONS_HW_VER_MASK = 0xf << 0,
281 VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4),
282 VERSIONS_SFP = BIT(5),
283 VERSIONS_VIDEO_MASK = 0x7 << 6,
284 VERSIONS_VIDEO_DVI = 0x0 << 6,
285 VERSIONS_VIDEO_DP_165 = 0x1 << 6,
286 VERSIONS_VIDEO_DP_300 = 0x2 << 6,
287 VERSIONS_VIDEO_HDMI = 0x3 << 6,
288 VERSIONS_UT_MASK = 0xf << 12,
289 VERSIONS_UT_MAIN_SERVER = 0x0 << 12,
290 VERSIONS_UT_MAIN_USER = 0x1 << 12,
291 VERSIONS_UT_VIDEO_SERVER = 0x2 << 12,
292 VERSIONS_UT_VIDEO_USER = 0x3 << 12,
293 };
294 u16 raw_versions;
295
296 memset(versions, 0, sizeof(struct fpga_versions));
297
298 FPGA_GET_REG(fpga, versions, &raw_versions);
299
300 switch (raw_versions & VERSIONS_UT_MASK) {
301 case VERSIONS_UT_MAIN_SERVER:
302 versions->video_channel = false;
303 versions->con_side = false;
304 break;
305
306 case VERSIONS_UT_MAIN_USER:
307 versions->video_channel = false;
308 versions->con_side = true;
309 break;
310
311 case VERSIONS_UT_VIDEO_SERVER:
312 versions->video_channel = true;
313 versions->con_side = false;
314 break;
315
316 case VERSIONS_UT_VIDEO_USER:
317 versions->video_channel = true;
318 versions->con_side = true;
319 break;
320
321 }
322
323 switch (raw_versions & VERSIONS_VIDEO_MASK) {
324 case VERSIONS_VIDEO_DVI:
325 versions->pcb_video_type = PCB_DVI_SL;
326 break;
327
328 case VERSIONS_VIDEO_DP_165:
329 versions->pcb_video_type = PCB_DP_165MPIX;
330 break;
331
332 case VERSIONS_VIDEO_DP_300:
333 versions->pcb_video_type = PCB_DP_300MPIX;
334 break;
335
336 case VERSIONS_VIDEO_HDMI:
337 versions->pcb_video_type = PCB_HDMI;
338 break;
339 }
340
341 versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
342
343 if (raw_versions & VERSIONS_SFP)
344 versions->pcb_transmission_type = PCB_FIBER_3G;
345 else
346 versions->pcb_transmission_type = PCB_CAT_1G;
347
348 return 0;
349 }
350
get_features(unsigned int fpga,struct fpga_features * features)351 static int get_features(unsigned int fpga, struct fpga_features *features)
352 {
353 enum {
354 FEATURE_CARRIER_SPEED_2_5 = BIT(4),
355 FEATURE_RAM_MASK = 0x7 << 5,
356 FEATURE_RAM_DDR2_32BIT = 0x0 << 5,
357 FEATURE_RAM_DDR3_32BIT = 0x1 << 5,
358 FEATURE_RAM_DDR3_48BIT = 0x2 << 5,
359 FEATURE_PCM_AUDIO_TX = BIT(9),
360 FEATURE_PCM_AUDIO_RX = BIT(10),
361 FEATURE_OSD = BIT(11),
362 FEATURE_USB20 = BIT(12),
363 FEATURE_COMPRESSION_MASK = 7 << 13,
364 FEATURE_COMPRESSION_TYPE1 = 0x1 << 13,
365 FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13,
366 FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13,
367 };
368
369 enum {
370 EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0),
371 EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1),
372 EXTENDED_FEATURE_RS232 = BIT(2),
373 EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3),
374 EXTENDED_FEATURE_INTERLACE = BIT(4),
375 };
376
377 u16 raw_features;
378 #ifdef GDSYS_LEGACY_DRIVERS
379 u16 raw_extended_features;
380 #endif
381
382 memset(features, 0, sizeof(struct fpga_features));
383
384 FPGA_GET_REG(fpga, fpga_features, &raw_features);
385 #ifdef GDSYS_LEGACY_DRIVERS
386 FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
387 #endif
388
389 features->video_channels = raw_features & 0x3;
390 features->carriers = (raw_features >> 2) & 0x3;
391
392 features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5)
393 ? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G;
394
395 switch (raw_features & FEATURE_RAM_MASK) {
396 case FEATURE_RAM_DDR2_32BIT:
397 features->ram_config = RAM_DDR2_32BIT_295MBPS;
398 break;
399
400 case FEATURE_RAM_DDR3_32BIT:
401 features->ram_config = RAM_DDR3_32BIT_590MBPS;
402 break;
403
404 case FEATURE_RAM_DDR3_48BIT:
405 features->ram_config = RAM_DDR3_48BIT_590MBPS;
406 break;
407 }
408
409 features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX;
410 features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX;
411 #ifdef GDSYS_LEGACY_DRIVERS
412 features->spdif_tx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_TX;
413 features->spdif_rx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_RX;
414 #endif
415
416 features->usb2 = raw_features & FEATURE_USB20;
417 #ifdef GDSYS_LEGACY_DRIVERS
418 features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232;
419 #endif
420
421 features->compression_type1 = false;
422 features->compression_type2 = false;
423 features->compression_type3 = false;
424 switch (raw_features & FEATURE_COMPRESSION_MASK) {
425 case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3:
426 features->compression_type3 = true;
427 case FEATURE_COMPRESSION_TYPE1_TYPE2:
428 features->compression_type2 = true;
429 case FEATURE_COMPRESSION_TYPE1:
430 features->compression_type1 = true;
431 break;
432 }
433
434 #ifdef GDSYS_LEGACY_DRIVERS
435 features->interlace = raw_extended_features & EXTENDED_FEATURE_INTERLACE;
436 #endif
437 features->osd = raw_features & FEATURE_OSD;
438 #ifdef GDSYS_LEGACY_DRIVERS
439 features->compression_pipes = raw_extended_features & EXTENDED_FEATURE_COMPRESSION_PIPES;
440 #endif
441
442 return 0;
443 }
444
445 #include <linux/bitops.h>
446 #endif
447
ioep_fpga_has_osd(unsigned int fpga)448 bool ioep_fpga_has_osd(unsigned int fpga)
449 {
450 struct fpga_features features;
451
452 get_features(fpga, &features);
453
454 return features.osd;
455 }
456
ioep_fpga_print_info(unsigned int fpga)457 void ioep_fpga_print_info(unsigned int fpga)
458 {
459 u16 fpga_version;
460 struct fpga_versions versions;
461 struct fpga_features features;
462
463 FPGA_GET_REG(fpga, fpga_version, &fpga_version);
464 get_versions(fpga, &versions);
465 get_features(fpga, &features);
466
467 if (versions.video_channel)
468 printf("Videochannel");
469 else
470 printf("Mainchannel");
471
472 if (versions.con_side)
473 printf(" User");
474 else
475 printf(" Server");
476
477 // FIXME
478 #if 0
479 if (versions & (1<<4))
480 printf(" UC");
481 #endif
482
483 switch(versions.pcb_transmission_type) {
484 case PCB_CAT_1G:
485 case PCB_CAT_10G:
486 printf(" CAT");
487 break;
488 case PCB_FIBER_3G:
489 case PCB_FIBER_10G:
490 printf(" Fiber");
491 break;
492 };
493
494 switch (versions.pcb_video_type) {
495 case PCB_DVI_SL:
496 printf(" DVI,");
497 break;
498 case PCB_DP_165MPIX:
499 printf(" DP 165MPix/s,");
500 break;
501 case PCB_DP_300MPIX:
502 printf(" DP 300MPix/s,");
503 break;
504 case PCB_HDMI:
505 printf(" HDMI,");
506 break;
507 case PCB_DP_1_2:
508 printf(" DP 1.2,");
509 break;
510 case PCB_HDMI_2_0:
511 printf(" HDMI 2.0,");
512 break;
513 }
514
515 printf(" FPGA V %d.%02d\n features: ",
516 fpga_version / 100, fpga_version % 100);
517
518 if (!features.compression_type1 &&
519 !features.compression_type2 &&
520 !features.compression_type3)
521 printf("no compression, ");
522
523 if (features.compression_type1)
524 printf("type1, ");
525
526 if (features.compression_type2)
527 printf("type2, ");
528
529 if (features.compression_type3)
530 printf("type3, ");
531
532 printf("%sosd", features.osd ? "" : "no ");
533
534 if (features.pcm_rx && features.pcm_tx)
535 printf(", pcm rx+tx");
536 else if(features.pcm_rx)
537 printf(", pcm rx");
538 else if(features.pcm_tx)
539 printf(", pcm tx");
540
541 if (features.spdif_rx && features.spdif_tx)
542 printf(", spdif rx+tx");
543 else if(features.spdif_rx)
544 printf(", spdif rx");
545 else if(features.spdif_tx)
546 printf(", spdif tx");
547
548 puts(",\n ");
549
550 switch (features.sysclock) {
551 case SYSCLK_147456:
552 printf("clock 147.456 MHz");
553 break;
554 }
555
556 switch (features.ram_config) {
557 case RAM_DDR2_32BIT_295MBPS:
558 printf(", RAM 32 bit DDR2");
559 break;
560 case RAM_DDR3_32BIT_590MBPS:
561 printf(", RAM 32 bit DDR3");
562 break;
563 case RAM_DDR3_48BIT_590MBPS:
564 case RAM_DDR3_48BIT_1800MBPS:
565 printf(", RAM 48 bit DDR3");
566 break;
567 case RAM_DDR3_64BIT_1800MBPS:
568 printf(", RAM 64 bit DDR3");
569 break;
570 }
571
572 printf(", %d carrier(s)", features.carriers);
573
574 switch(features.carrier_speed) {
575 case CARRIER_SPEED_1G:
576 printf(", 1Gbit/s");
577 break;
578 case CARRIER_SPEED_3G:
579 printf(", 3Gbit/s");
580 break;
581 case CARRIER_SPEED_10G:
582 printf(", 10Gbit/s");
583 break;
584 }
585
586 printf(", %d video channel(s)\n", features.video_channels);
587 }
588
589 #endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
590