1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (C) 2013 Imagination Technologies
5 */
6
7 #include <config.h>
8 #include <fdt_support.h>
9 #include <init.h>
10 #include <net.h>
11 #include <netdev.h>
12 #include <pci.h>
13 #include <pci_gt64120.h>
14 #include <pci_msc01.h>
15 #include <rtc.h>
16 #include <asm/global_data.h>
17 #include <linux/delay.h>
18
19 #include <asm/addrspace.h>
20 #include <asm/io.h>
21 #include <asm/malta.h>
22
23 #include "superio.h"
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 #define MALTA_GT_PATH "/pci0@1be00000"
28 #define MALTA_MSC_PATH "/pci0@1bd00000"
29
30 enum core_card {
31 CORE_UNKNOWN,
32 CORE_LV,
33 CORE_FPGA6,
34 };
35
36 enum sys_con {
37 SYSCON_UNKNOWN,
38 SYSCON_GT64120,
39 SYSCON_MSC01,
40 };
41
malta_lcd_puts(const char * str)42 static void malta_lcd_puts(const char *str)
43 {
44 int i;
45 void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
46
47 /* print up to 8 characters of the string */
48 for (i = 0; i < min((int)strlen(str), 8); i++) {
49 __raw_writel(str[i], reg);
50 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
51 }
52
53 /* fill the rest of the display with spaces */
54 for (; i < 8; i++) {
55 __raw_writel(' ', reg);
56 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
57 }
58 }
59
malta_core_card(void)60 static enum core_card malta_core_card(void)
61 {
62 u32 corid, rev;
63 const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION);
64
65 rev = __raw_readl(reg);
66 corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
67
68 switch (corid) {
69 case MALTA_REVISION_CORID_CORE_LV:
70 return CORE_LV;
71
72 case MALTA_REVISION_CORID_CORE_FPGA6:
73 return CORE_FPGA6;
74
75 default:
76 return CORE_UNKNOWN;
77 }
78 }
79
malta_sys_con(void)80 static enum sys_con malta_sys_con(void)
81 {
82 switch (malta_core_card()) {
83 case CORE_LV:
84 return SYSCON_GT64120;
85
86 case CORE_FPGA6:
87 return SYSCON_MSC01;
88
89 default:
90 return SYSCON_UNKNOWN;
91 }
92 }
93
dram_init(void)94 int dram_init(void)
95 {
96 gd->ram_size = CFG_SYS_SDRAM_SIZE;
97
98 return 0;
99 }
100
checkboard(void)101 int checkboard(void)
102 {
103 enum core_card core;
104
105 malta_lcd_puts("U-Boot");
106 puts("Board: MIPS Malta");
107
108 core = malta_core_card();
109 switch (core) {
110 case CORE_LV:
111 puts(" CoreLV");
112 break;
113
114 case CORE_FPGA6:
115 puts(" CoreFPGA6");
116 break;
117
118 default:
119 puts(" CoreUnknown");
120 }
121
122 putc('\n');
123 return 0;
124 }
125
126 #if !IS_ENABLED(CONFIG_DM_ETH)
board_eth_init(struct bd_info * bis)127 int board_eth_init(struct bd_info *bis)
128 {
129 return pci_eth_init(bis);
130 }
131 #endif
132
_machine_restart(void)133 void _machine_restart(void)
134 {
135 void __iomem *reset_base;
136
137 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
138 __raw_writel(GORESET, reset_base);
139 mdelay(1000);
140 }
141
board_early_init_f(void)142 int board_early_init_f(void)
143 {
144 ulong io_base;
145
146 /* choose correct PCI I/O base */
147 switch (malta_sys_con()) {
148 case SYSCON_GT64120:
149 io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
150 break;
151
152 case SYSCON_MSC01:
153 io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
154 break;
155
156 default:
157 return -1;
158 }
159
160 set_io_port_base(io_base);
161
162 /* setup FDC37M817 super I/O controller */
163 malta_superio_init();
164
165 return 0;
166 }
167
misc_init_r(void)168 int misc_init_r(void)
169 {
170 rtc_reset();
171
172 return 0;
173 }
174
175 #if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
176 /*
177 * TODO: currently doesn't work because rw_fdt_blob points to a
178 * NOR flash address. This needs some changes in board_init_f.
179 */
board_fix_fdt(void * rw_fdt_blob)180 int board_fix_fdt(void *rw_fdt_blob)
181 {
182 int node = -1;
183
184 switch (malta_sys_con()) {
185 case SYSCON_GT64120:
186 node = fdt_path_offset(rw_fdt_blob, MALTA_GT_PATH);
187 break;
188 default:
189 case SYSCON_MSC01:
190 node = fdt_path_offset(rw_fdt_blob, MALTA_MSC_PATH);
191 break;
192 }
193
194 return fdt_status_okay(rw_fdt_blob, node);
195 }
196 #endif
197
board_early_init_r(void)198 int board_early_init_r(void)
199 {
200 struct udevice *dev;
201 int ret;
202
203 pci_init();
204
205 ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL,
206 PCI_DEVICE_ID_INTEL_82371AB_0, 0, &dev);
207 if (ret)
208 panic("Failed to find PIIX4 PCI bridge\n");
209
210 /* setup PCI interrupt routing */
211 dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCA, 10);
212 dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCB, 10);
213 dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCC, 11);
214 dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCD, 11);
215
216 /* mux SERIRQ onto SERIRQ pin */
217 dm_pci_clrset_config32(dev, PCI_CFG_PIIX4_GENCFG, 0,
218 PCI_CFG_PIIX4_GENCFG_SERIRQ);
219
220 /* enable SERIRQ - Linux currently depends upon this */
221 dm_pci_clrset_config8(dev, PCI_CFG_PIIX4_SERIRQC, 0,
222 PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT);
223
224 ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL,
225 PCI_DEVICE_ID_INTEL_82371AB, 0, &dev);
226 if (ret)
227 panic("Failed to find PIIX4 IDE controller\n");
228
229 /* enable bus master & IO access */
230 dm_pci_clrset_config32(dev, PCI_COMMAND, 0,
231 PCI_COMMAND_MASTER | PCI_COMMAND_IO);
232
233 /* set latency */
234 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
235
236 /* enable IDE/ATA */
237 dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_PRI,
238 PCI_CFG_PIIX4_IDETIM_IDE);
239 dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_SEC,
240 PCI_CFG_PIIX4_IDETIM_IDE);
241
242 return 0;
243 }
244