1 // SPDX-License-Identifier: GPL-2.0+
2
3 #include <config.h>
4 #include <errno.h>
5 #include <fsl_esdhc_imx.h>
6 #include <hang.h>
7 #include <init.h>
8 #include <log.h>
9 #include <spl.h>
10 #include <asm/arch/ddr.h>
11 #include <asm/arch/imx8mq_pins.h>
12 #include <asm/arch/sys_proto.h>
13 #include <asm/arch/clock.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/gpio.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <asm/sections.h>
20 #include <linux/delay.h>
21 #include <power/pmic.h>
22 #include <power/pfuze100_pmic.h>
23
24 #include "pitx_misc.h"
25
26 extern struct dram_timing_info dram_timing_2gb;
27 extern struct dram_timing_info dram_timing_4gb;
28
29 DECLARE_GLOBAL_DATA_PTR;
30
spl_dram_init(void)31 static void spl_dram_init(void)
32 {
33 struct dram_timing_info *dram_timing;
34 int variant = 0, size;
35
36 variant = get_pitx_board_variant();
37
38 switch(variant) {
39 case 2:
40 dram_timing = &dram_timing_2gb;
41 size = 2;
42 break;
43 case 3:
44 dram_timing = &dram_timing_4gb;
45 size = 4;
46 break;
47 default:
48 printf("Unknown DDR type (%d)\n", variant);
49 return;
50 };
51
52 /* ddr init */
53 ddr_init(dram_timing);
54 }
55
56 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
57 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
58 static struct i2c_pads_info i2c_pad_info1 = {
59 .scl = {
60 .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
61 .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
62 .gp = IMX_GPIO_NR(5, 14),
63 },
64 .sda = {
65 .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
66 .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
67 .gp = IMX_GPIO_NR(5, 15),
68 },
69 };
70
71 #if CONFIG_IS_ENABLED(MMC)
72 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
73 #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
74 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
75
board_mmc_getcd(struct mmc * mmc)76 int board_mmc_getcd(struct mmc *mmc)
77 {
78 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
79
80 switch (cfg->esdhc_base) {
81 case USDHC1_BASE_ADDR:
82 /* the eMMC does not have a CD pin */
83 return 1;
84 case USDHC2_BASE_ADDR:
85 return !gpio_get_value(USDHC2_CD_GPIO);
86 }
87
88 return 0;
89 }
90
91 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
92 PAD_CTL_FSEL2)
93 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
94
95 static iomux_v3_cfg_t const usdhc1_pads[] = {
96 IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97 IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
98 IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
99 IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
100 IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
101 IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
102 IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103 IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
107 };
108
109 static iomux_v3_cfg_t const usdhc2_pads[] = {
110 IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
111 IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
112 IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
113 IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
114 IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
115 IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
116 IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
117 IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
118 };
119
120 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
121 {USDHC1_BASE_ADDR, 0, 8},
122 {USDHC2_BASE_ADDR, 0, 4},
123 };
124
board_mmc_init(struct bd_info * bis)125 int board_mmc_init(struct bd_info *bis)
126 {
127 int i, ret;
128 /*
129 * According to the board_mmc_init() the following map is done:
130 * (U-Boot device node) (Physical Port)
131 * mmc0 USDHC1
132 * mmc1 USDHC2
133 */
134 for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
135 switch (i) {
136 case 0:
137 init_clk_usdhc(0);
138 usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
139 imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
140 ARRAY_SIZE(usdhc1_pads));
141 gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
142 gpio_direction_output(USDHC1_PWR_GPIO, 0);
143 udelay(500);
144 gpio_direction_output(USDHC1_PWR_GPIO, 1);
145 break;
146 case 1:
147 init_clk_usdhc(1);
148 usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
149 imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
150 ARRAY_SIZE(usdhc2_pads));
151 gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
152 gpio_direction_output(USDHC2_PWR_GPIO, 0);
153 udelay(500);
154 gpio_direction_output(USDHC2_PWR_GPIO, 1);
155 break;
156 default:
157 printf("Warning: you configured more USDHC controllers "
158 "(%d) than supported by the board\n", i + 1);
159 return -EINVAL;
160 }
161
162 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
163 if (ret)
164 return ret;
165 }
166
167 return 0;
168 }
169
spl_board_loader_name(u32 boot_device)170 const char *spl_board_loader_name(u32 boot_device)
171 {
172 switch (boot_device) {
173 case BOOT_DEVICE_MMC1:
174 return "eMMC";
175 case BOOT_DEVICE_MMC2:
176 return "SD card";
177 default:
178 return NULL;
179 }
180 }
181 #endif
182
183 #if CONFIG_IS_ENABLED(POWER_LEGACY)
184 #define I2C_PMIC 0
185
pfuze_mode_init(struct pmic * p,u32 mode)186 static int pfuze_mode_init(struct pmic *p, u32 mode)
187 {
188 unsigned char offset, i, switch_num;
189 u32 id;
190 int ret;
191
192 pmic_reg_read(p, PFUZE100_DEVICEID, &id);
193 id = id & 0xf;
194
195 if (id == 0) {
196 switch_num = 6;
197 offset = PFUZE100_SW1CMODE;
198 } else if (id == 1) {
199 switch_num = 4;
200 offset = PFUZE100_SW2MODE;
201 } else {
202 printf("Not supported, id=%d\n", id);
203 return -EINVAL;
204 }
205
206 ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
207 if (ret < 0) {
208 printf("Set SW1AB mode error!\n");
209 return ret;
210 }
211
212 for (i = 0; i < switch_num - 1; i++) {
213 ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
214 if (ret < 0) {
215 printf("Set switch 0x%x mode error!\n",
216 offset + i * SWITCH_SIZE);
217 return ret;
218 }
219 }
220
221 return ret;
222 }
223
power_init_board(void)224 int power_init_board(void)
225 {
226 struct pmic *p;
227 int ret;
228 unsigned int reg;
229
230 ret = power_pfuze100_init(I2C_PMIC);
231 if (ret)
232 return -ENODEV;
233
234 p = pmic_get("PFUZE100");
235 ret = pmic_probe(p);
236 if (ret)
237 return -ENODEV;
238
239 pmic_reg_read(p, PFUZE100_SW3AVOL, ®);
240 if ((reg & 0x3f) != 0x18) {
241 reg &= ~0x3f;
242 reg |= 0x18;
243 pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
244 }
245
246 ret = pfuze_mode_init(p, APS_PFM);
247 if (ret < 0)
248 return ret;
249
250 /* set SW3A standby mode to off */
251 pmic_reg_read(p, PFUZE100_SW3AMODE, ®);
252 reg &= ~0xf;
253 reg |= APS_OFF;
254 pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
255
256 return 0;
257 }
258 #endif
259
board_init_f(ulong dummy)260 void board_init_f(ulong dummy)
261 {
262 int ret;
263
264 /* Clear global data */
265 memset((void *)gd, 0, sizeof(gd_t));
266
267 arch_cpu_init();
268
269 init_uart_clk(2);
270
271 board_early_init_f();
272
273 timer_init();
274
275 preloader_console_init();
276
277 /* Clear the BSS. */
278 memset(__bss_start, 0, __bss_end - __bss_start);
279
280 ret = spl_init();
281 if (ret) {
282 debug("spl_init() failed: %d\n", ret);
283 hang();
284 }
285
286 enable_tzc380();
287
288 setup_i2c(0, 100000, 0x7f, &i2c_pad_info1);
289
290 #if CONFIG_IS_ENABLED(POWER_LEGACY)
291 power_init_board();
292 #endif
293
294 spl_dram_init();
295
296 board_init_r(NULL, 0);
297 }
298